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1 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer description ------table of contents------ description the m16c/62t group of single-chip microcomputers are built using the high-performance silicon gate cmos process using a m16c/60 series cpu core and are packaged in a 100-pin or a 80-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, they are capable of executing instructions at high speed. they also feature a built-in multiplier and dmac, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. the m16c/62t group includes a wide range of products with different internal memory types and sizes and various package types. features ? memory capacity .................................. m30623m4t-xxxgp : rom 32k bytes, ram 3k bytes m30622m8t/m8v-xxxfp,m30623m8t/m8v-xxxgp : rom 64k bytes, ram 4k bytes m30622mct/mcv-xxxfp,m30623mct/mcv-xxxgp : rom 128k bytes, ram 5k bytes m30622ect/ecv-xxxfp,m30623ect/ecv-xxxgp : prom 128k bytes, ram 5k bytes ? shortest instruction execution time ......62.5ns (f(x in )=16mh z , v cc =5v) ? supply voltage ..................................... mask rom version : 4.2 to 5.5v (f(x in )=16mh z , without software wait) one-time prom version : 4.5 to 5.5v (f(x in )=16mh z , without software wait) ? low power consumption ......................140mw (v cc = 5v, f(x in )=16mh z ) ? interrupts 25 internal interrupt sources, 8 external interrupt sources (m30622(100-pin package)) /5 sources (m30623(80-pin package)), 4 software interrupt sources, 7 levels (including key input interrupt) ? multifunction 16-bit timer ...................... 5 i/o timers + 6 input timers(m30622(100-pin package)) 3 i/o timers + 5 input timers(m30623(80-pin package)) ? inside 16-bit timer ................................ 3 timers(only m30623(80-pin package))(note 1) ? serial i/o .............................................. ? m30622(100-pin package) : 3 for uart or clock synchronous + 2 for synchronous ? m30623(80-pin package) : 3 for uart or clock synchronous(one of exclusive uart) + 2 for synchronous(one of exclusive transmission) ? dmac .................................................. 2 channels (trigger: 24 sources) ? a-d converter ....................................... 10 bits x 8 channels (expandable up to 26 channels) ? d-a converter ....................................... 8 bits x 2 channels ? crc calculation circuit ......................... 1 circuit ? watchdog timer ....................................1 line ? programmable i/o ............................... 87 lines(m30622(100-pin package)),70 lines(m30623(80-pin package)) ? input port.............................................. _______ 1 line (p8 5 shared with nmi pin) ? memory expansion .............................. available (to 1.2m bytes or 4m bytes) ? chip select output ................................ 4 lines(only m30622(100-pin package))(note 2) ? clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) note 1: in m30623(80-pin package), these timers have no corresponding external pin can be used as internal timers. note 2: m30623(80-pin package) has no external pin for chip select output. applications audio, cameras, office equipment, communications equipment, portable equipment, cars, etc central processing unit (cpu) ..................... 12 reset ............................................................. 15 processor mode ............................................ 28 clock generating circuit ............................... 40 protection ...................................................... 49 interrupts ....................................................... 50 watchdog timer ............................................ 70 dmac ........................................................... 72 specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. timer ............................................................. 82 timers function for three-phase motor control .......... 100 serial i/o ..................................................... 112 a-d converter ............................................. 146 d-a converter ............................................. 157 crc calculation circuit .............................. 159 programmable i/o ports ............................. 161 electrical characteristics ............................. 176
mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer 2 description 80 79 p1 0 /d 8 p1 1 /d 9 78 77 p1 2 /d 10 p1 3 /d 11 76 75 p1 4 /d 12 p1 5 /d 13 /int 3 74 73 p1 6 /d 14 /int 4 p1 7 /d 15 /int 5 72 71 p2 0 /an 20 /a 0 (/d 0 /-) p2 1 /an 21 /a 1 (/d 1 /d 0 ) 70 69 p2 2 /an 22 /a 2 (/d 2 /d 1 ) p2 3 /an 23 /a 3 (/d 3 /d 2 ) 68 67 p2 4 /an 24 /a 4 (/d 4 /d 3 ) p2 5 /an 25 /a 5 (/d 5 /d 4 ) 66 65 p2 6 /an 26 /a 6 (/d 6 /d 5 ) p2 7 /an 27 /a 7 (/d 7 /d 6 ) 64 63 v ss p3 0 /a 8 (/-/d 7 ) 62 61 v cc p3 1 /a 9 60 59 p3 2 /a 10 p3 3 /a 11 58 57 p3 4 /a 12 p3 5 /a 13 56 55 p3 6 /a 14 p3 7 /a 15 54 53 p4 0 /a 16 p4 1 /a 17 52 51 p4 2 /a 18 p4 3 /a 19 50 p4 4 /cs0 49 p4 5 /cs1 48 p4 6 /cs2 47 p4 7 /cs3 46 p5 0 /wrl/wr 45 p5 1 /wrh/bhe 44 p5 2 /rd 43 p5 3 /bclk 42 p5 4 /hlda 41 p5 5 /hold 40 p5 6 /ale 39 p5 7 /rdy/clk out 38 p6 0 /cts 0 /rts 0 37 p6 1 /clk 0 36 p6 2 /rxd 0 35 p6 3 /txd 0 34 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 33 p6 5 /clk 1 32 p6 6 /rxd 1 31 p6 7 /txd 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p9 5 /anex0/clk 4 p9 4 /da 1 /tb4 in p9 3 /da 0 /tb3 in p9 2 /tb2 in /s out3 p9 1 /tb1 in /s in3 p9 0 /tb0 in /clk 3 byte cnv ss p8 7 /x cin p8 6 /x cout reset x out v ss x in v cc p8 5 /nmi p8 4 /int 2 p8 3 /int 1 p8 2 /int 0 p8 1 /ta4 in /u p8 0 /ta4 out /u p7 7 /ta3 in p7 6 /ta3 out p7 5 /ta2 in /w p7 4 /ta2 out /w p7 3 /cts 2 /rts 2 /ta1 in /v p7 2 /clk 2 /ta1 out /v p7 1 /rxd 2 /scl/ta0 in /tb5 in p7 0 /txd 2 /sda/ta0 out 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 p0 7 /an 07 /d 7 p0 6 /an 06 /d 6 p0 5 /an 05 /d 5 p0 4 /an 04 /d 4 p0 3 /an 03 /d 3 p0 2 /an 02 /d 2 p0 1 /an 01 /d 1 p0 0 /an 00 /d 0 p10 7 /an 7 /ki 3 p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4 /ki 0 p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 av ss p10 0 /an 0 v ref p9 7 /ad trg /s in4 p9 6 /anex1/s out4 av cc m16c/62t group pin configuration figures 1.1.1 show the pin configurations (top view) of m30622(100-pin package) and 1.1.2 show the pin configurations (top view) of m30623(80-pin package). pin configuration (top view) figure 1.1.1. pin configuration (top view) of m30622 (100-pin package) package: 100p6s-a
3 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer description 60 59 58 57 56 55 54 53 52 51 p2 0 /an 20 /a 0 (/d 0 ) p2 1 /an 21 /a 1 (/d 1 ) 50 49 p2 2 /an 22 /a 2 (/d 2 ) p2 3 /an 23 /a 3 (/d 3 ) 48 47 p2 4 /an 24 /a 4 (/d 4 ) p2 5 /an 25 /a 5 (/d 5 ) 46 45 p2 6 /an 26 /a 6 (/d 6 ) p2 7 /an 27 /a 7 (/d 7 ) 44 43 p3 0 /a 8 42 41 p3 1 /a 9 p3 2 /a 10 p3 3 /a 11 p3 4 /a 12 p3 5 /a 13 p3 6 /a 14 p3 7 /a 15 p4 0 /a 16 p4 1 /a 17 p4 2 /a 18 40 39 38 37 36 p5 0 /wrl/wr 35 p5 1 /wrh/bhe 34 p5 2 /rd 33 p5 3 /bclk 32 p5 4 /hlda 31 p5 5 /hold 30 p5 6 /ale 29 p5 7 /rdy/clk out 28 p6 0 /cts 0 /rts 0 27 p6 1 /clk 0 26 p6 2 /rxd 0 25 p6 3 /txd 0 24 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 23 p6 5 /clk 1 22 p6 6 /rxd 1 21 p6 7 /txd 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 p9 5 /anex0/clk 4 p9 4 /da 1 /tb4 in p9 3 /da 0 /tb3 in p9 2 /tb2 in /s out3 p9 0 /tb0 in /clk 3 cnv ss (byte) p8 7 /x cin p8 6 /x cout reset x out v ss x in v cc p8 5 /nmi p8 4 /int 2 p8 3 /int 1 p8 2 /int 0 p8 1 /ta4 in p8 0 /ta4 out p7 7 /ta3 in 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p0 6 /an 06 /d 6 p0 5 /an 05 /d 5 p0 4 /an 04 /d 4 p0 3 /an 03 /d 3 p0 2 /an 02 /d 2 p0 1 /an 01 /d 1 p0 0 /an 00 /d 0 p10 7 /an 7 /ki 3 p10 6 /an 6 /ki 2 p10 5 /an 5 /ki 1 p10 4 /an 4 /ki 0 p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 av ss p10 0 /an 0 v ref p9 7 /ad trg /s in4 av cc m16c/62t group p9 6 /anex1/s out4 p7 0 /txd 2 /sda/ta0 out p7 1 /rxd 2 /scl/ta0 in /tb5 in p7 6 /ta3 out p4 3 /a 19 p0 7 /an 07 /d 7 figure 1.1.2. pin configuration (top view) of m30623 (80-pin package) package: 80p6s-a pin configuration (top view)
mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer 4 description block diagram figure 1.1.3 is block diagrams of m30622(100-pin package) and 1.1.4 is block diagrams of m30623(80-pin package). i/o ports port p0 8 port p1 8 port p2 8 port p3 8 port p4 8 port p5 8 port p6 8 port p7 8 port p8 7 port p8 5 port p9 8 port p10 8 internal peripheral functions timer timer ta0 (16 bits) timer ta1 (16 bits) timer ta2 (16 bits) timer ta3 (16 bits) timer ta4 (16 bits) timer tb0 (16 bits) timer tb1 (16 bits) timer tb2 (16 bits) timer tb3 (16 bits) timer tb4 (16 bits) timer tb5 (16 bits) watchdog timer (15 bits) dmac (2 channels) d-a converter (8 bits 5 2 channels) sb registers program conter r0h r0l r1h r1l r2 r3 a0 a1 fb pc sutack pointer isp usp vector table intb flg m16c/60series 16-bit cpu core memory multiplier a-d converter (10 bits 5 8 channels expandable up to 26 channels) uart/clock synchronous si/o (8 bits 5 3 channels) (note 1) crc arithmetic circuit (ccitt) (polynominal: x 16 +x 12 +x 5 +1) system clock generator x in -x out x cin -x cout clock synchronous si/o (8 bits 5 2 channels) rom (note 2) ram (note 3) r0h r0l r1h r1l r2 r3 a0 a1 fb note 1: one of 3 channels also functions as iic bus interface. note 2: rom size depends on mcu type. note 3: ram size depends on mcu type. figure 1.1.3. block diagram of m30622 (100-pin package)
5 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer description figure 1.1.4. block diagram of m30623 (80-pin package) i/o ports port p0 8 port p2 8 port p3 8 port p4 4 port p5 8 port p6 8 port p7 4 port p8 7 port p8 5 port p9 7 port p10 8 internal peripheral functions timer timer ta0 (16 bits) timer ta1 (16 bits) timer ta2 (16 bits) timer ta3 (16 bits) timer ta4 (16 bits) timer tb0 (16 bits) timer tb1 (16 bits) timer tb2 (16 bits) timer tb3 (16 bits) timer tb4 (16 bits) timer tb5 (16 bits) watchdog timer (15 bits) dmac (2 channels) d-a converter (8 bits 5 2 channels) sb registers program conter r0h r0l r1h r1l r2 r3 a0 a1 fb pc sutack pointer isp usp vector table intb flg m16c/60series 16-bit cpu core memory multiplier a-d converter (10 bits 5 8 channels expandable up to 26 channels) uart/clock synchronous si/o (8 bits 5 3 channels) (note 1) crc arithmetic circuit (ccitt) (polynominal: x 16 +x 12 +x 5 +1) system clock generator x in -x out x cin -x cout clock synchronous si/o (8 bits 5 2 channels) (note 2) rom (note 3) ram (note 4) r0h r0l r1h r1l r2 r3 a0 a1 fb note 1: one of 3 channels is an exclusive uart, functions as iic bus interface. note 2: one of 3 channels is an exclusive transmission. note 3: rom size depends on mcu type. note 4: ram size depends on mcu type.
mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer 6 description performance outline table 1.1.1 is a performance outline of m16c/62t group. item performance m30622(100-pin package) m30623(80-pin package) number of basic instructions 91 instructions shortest instruction execution time 62.5ns(f(x in )=16mh z , v cc =5v) memory rom 32kbytes (m30623m4t-xxxgp) capacity 64kbytes (m30622m8t/m8v-xxxfp, m30623m8t/m8v-xxxgp) 128kbytes (m30622mct/mcv-xxxfp, m30623mct/mcv-xxxgp, m30622ect/ecv-xxxfp, m30623ect/ecv-xxxgp) ram 3kbytes (m30623m4t-xxxgp) 4kbytes (m30622m8t/m8v-xxxfp, m30623m8t/m8v-xxxgp) 5kbytes (m30622mct/mcv-xxxfp, m30623mct/mcv-xxxgp, m30622ect/ecv-xxxfp, m30623ect/ecv-xxxgp) i/o port p0, p2, p3, p5, p6, p10 8 bits x 6 p1 8 bits x 1 - p4, p7 8 bits x 2 4 bits x 2 p8 (except p8 5 ) 7 bits x 1 p9 8 bits x 1 7 bits x 1 input port p8 5 1 bit x 1 multifunction ta0, a3, ta4 16 bits x 3 (cycle timer, external / internal event count, pulse output) timer ta1, ta2 16 bits x 2 16 bits x 2 (cycle timer, external / internal event count, pulse output) (cycle timer, internal event count) tb0, tb2 to tb5 16 bits x 5 (cycle timer, external / internal event count, pulse period / pulse width measurement) tb1 16 bits x 1 (cycle timer, external / internal event 16 bits x 1 count, pulse period / pulse width measurement) (cycle timer, internal event count) serial i/o uart0, uart1 (uart or clock synchronous) x 2 uart2 (uart or clock synchronous) x 1 uart x 1 si/o3 (clock synchronous) x 1 (clock synchronous) x 1 (exclusive transmission) si/o4 (clock synchronous) x 1 a-d converter 10 bits x (8 x 3 + 2) channels d-a converter 8 bits x 2 channels dmac 2 channels (trigger: 24 sources) crc calculation circuit crc-ccitt watchdog timer 15 bits x 1 (with prescaler) interrupt 25 internal and 8 external sources, 25 internal and 5 external sources, 4 software sources, 7 levels 4 software sources, 7 levels clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) supply voltage mask rom version : 4.2 to 5.5v (f(x in )=16mh z , without software wait) one-time prom version : 4.5 to 5.5v (f(x in )=16mh z , without software wait) power consumption 140mw (v cc =5v, f(x in ) = 16mh z ) i/o i/o withstand voltage 5v characteristics output current 5ma memory expansion available (to 1.2m bytes or 4m bytes) (the m16c/62t group is not guaranteed to operate in memory expansion.) operating ambient temperature 85 c guaranteed version : -40 c to 85 c, 125 c guaranteed version : -40 c to 125 c device configuration cmos high performance silicon gate package 100-pin plastic mold qfp 80-pin plastic mold qfp table 1.1.1. performance outline of m16c/62t group
7 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer description mitsubishi plans to release the following products in the m16c/62t group: (1) support for mask rom version, one-time prom version one-time prom version has the equally functions mask rom version, with the exception of built-in electolic-programming-possible prom. (2) rom capacity (3) package(number of pin) 100p6s-a : 100-pin plastic molded qfp 80p6s-a : 80-pin plastic molded qfp (4) support for 85 c guaranteed version, 125 c guaranteed version 125 c guaranteed version m30622mxv/ecv-xxxfp, m30623mxv/ecv-xxxgp is suported. these are different from 85 c guaranteed version m30622mxt/ect-xxxfp, m30623mxt/ect-xxxgp on operating ambient temperature and the terms of the use, and so please inquire. 100-pin packaege 64k bytes 128k bytes mask rom version one-time prom version rom size m30623m8t-xxxgp m30623m8v-xxxgp m30623mct-xxxgp m30623mcv-xxxgp \ shipped in blank m30622mct-xxxfp m30622mcv-xxxfp m30622m8t-xxxfp m30622m8v-xxxfp m30622ect-xxxfp m30622ectfp m30622ecv-xxxfp m30622ecvfp 80-pin packaege \ \ m30623ect-xxxgp m30623ectgp m30623ecv-xxxgp m30623ecvgp 32k bytes m30623m4t-xxxgp \ \ mask rom version one-time prom version note 1: it may change in the future. note 2: use shipped in blank of one-time prom version as the trial, development of program. in case of vehicle-mount test or mass production, use shipped in programming. figure 1.1.5. rom expansion now: mar.1999.
mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer 8 description the m16c/62t group products currently supported are listed in table 1.1.2. type no. package remarks m30622mct-xxxfp m30622ect-xxxfp m30622ectfp 128k bytes mask rom version one-time prom version (programming) one-time prom version (blank) 100p6s-a m30622mcv-xxxfp m30622ecv-xxxfp m30622ecvfp m30623mct-xxxgp m30623ect-xxxgp m30623ectgp 128k bytes 80p6s-a characteristic 5k bytes 5k bytes m30623mcv-xxxgp m30623ecv-xxxgp m30623ecvgp m30622m8t-xxxfp m30622m8v-xxxfp 64k bytes mask rom version 85 ? guaranteed version 4k bytes m30623m4t-xxxgp m30623m8t-xxxgp m30623m8v-xxxgp 125 ? guaranteed version (note 3) 64k bytes 4k bytes 32k bytes 3k bytes rom capacity ram capacity 85 ? guaranteed version 85 ? guaranteed version 85 ? guaranteed version 85 ? guaranteed version 125 ? guaranteed version (note 3) 125 ? guaranteed version (note 3) 125 ? guaranteed version (note 3) mask rom version mask rom version mask rom version mask rom version mask rom version one-time prom version (programming) one-time prom version (blank) one-time prom version (programming) one-time prom version (blank) one-time prom version (programming) one-time prom version (blank) table 1.1.2. m16c/62t group now: mar.1999. type no. m30 62 2 m c t xxx fp package type fp : package 100p6s-a gp : 80p6s-a rom no. omitted for blank one-time prom version and eprom version rom capacity 4 : 32k bytes 8 : 64k bytes c : 128k bytes memory type m : mask rom version e : eprom or one-time prom version shows ram capacity, pin count, etc (the value itself has no specific meaning) m16c family m16c/62 group characteristic t : 85 ? guaranteed version for automobile v : 125 ? guaranteed version for automobile figure 1.1.6. type no., memory size, and package note 1: it may change in the future. note 2: use shipped in blank of one-time prom version as the trial, development of program. in case of vehicle-mount test or mass production, use shipped in programming. note 3: it is different from 85 c guaranteed version on operating ambient temperature and the terms of the use, pleas inquire.
tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development 9 pin description pin description pin name v cc , v ss cnv ss ____________ reset x in x out byte av cc av ss v ref p0 0 to p0 7 d 0 to d 7 p1 0 to p1 7 d 8 to d 15 p2 0 to p2 7 a 0 to a 7 a 0 /d 0 to a 7 /d 7 a 0 , a 1 /d 0 to a 7 /d 6 p3 0 to p3 7 a 8 to a 15 a 8 /d 7 , a 9 to a 15 signal name power supply input cnv ss reset input clock input clock output external data bus width select input analog power supply input analog power supply input reference voltage input i/o port p0 i/o port p1 i/o port p2 i/o port p3 i/o type input input input output input input input/output input/output input/output input/output input/output output input/output output input/output input/output output input/output function supply 4.2 v to 5.5 v to the v cc pin. supply 0 v to the v ss pin. this pin switches between processor modes. connect it to the v ss pin when operating in single-chip or memory expansion mode. connect it to the v cc pin when operating in microprocessor mode. a l on this input resets the microcomputer. these pins are provided for the main clock generating circuit. connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. this pin selects the width of an external data bus. a 16-bit width is selected when this input is l; an 8-bit width is selected when this input is h. this input must be fixed to either h or l. when operating in single-chip mode, connect this pin to v ss . in m30623 (80-pin package), the byte signal is internally connected to the cnv ss signal. this pin is a power supply input for the a-d converter. connect this pin to v cc . this pin is a power supply input for the a-d converter. connect this pin to v ss . this pin is a reference voltage input for the a-d converter. this is an 8-bit cmos i/o port. it has an input/output port direction register that allows the user to set each pin for input or output individually. when set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. pins in this port also function as a-d converter extended input pins as selected by software when operating in single-chip mode. when set as a separate bus, these pins input and output data (d 0 Cd 7 ). this is an 8-bit i/o port equivalent to p0. pins in this port also function as external interrupt pins as selected by software. when set as a separate bus, these pins input and output data (d 8 Cd 15 ). this is an 8-bit i/o port equivalent to p0. pins in this port also function as a-d converter extended input pins as selected by software when operating in single-chip mode. these pins output 8 low-order address bits (a 0 Ca 7 ). if the external bus is set as an 8-bit wide multiplexed bus, these pins input and output data (d 0 Cd 7 ) and output 8 low-order address bits (a 0 Ca 7 ) separated in time by multiplexing. if the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (d 0 Cd 6 ) and output address (a 1 Ca 7 ) separated in time by multiplexing. they also output address (a 0 ). this is an 8-bit i/o port equivalent to p0. these pins output 8 middle-order address bits (a 8 Ca 15 ). if the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (d 7 ) and output address (a 8 ) separated in time by multiplexing. they also output address (a 9 Ca 15 ).
tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development 10 pin description pin description pin name p4 0 to p4 7 ______ ______ cs 0 to cs 3 , a 16 to a 19 p5 0 to p5 7 ________ ______ wrl/wr, _________ _______ wrh/bhe, rd, bclk, __________ hlda, __________ hold, ale, ________ rdy p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 4 , p8 6 , p8 7 , p8 5 p9 0 to p9 7 p10 0 to p10 7 signal name i/o port p4 i/o port p5 i/o port p6 i/o port p7 i/o port p8 i/o port p8 5 i/o port p9 i/o port p10 i/o type input/output output output input/output output output output output output input output input input/output input/output input/output input/output input/output input input/output input/output function this is an 8-bit i/o port equivalent to p0. ______ ______ _______ _______ these pins output cs 0 Ccs 3 signals and a 16 Ca 19 . cs 0 Ccs 3 are chip select signals used to specify an access space. a 16 Ca 19 are 4 high-order address bits. this is an 8-bit i/o port equivalent to p0. in single-chip mode, p5 7 in this port outputs a divide-by-8 or divide-by-32 clock of x in or a clock of the same frequency as x cin as selected by software. ________ ________ ______ _______ _____ __________ output wrl, wrh (wr and bhe), rd, bclk, hlda, and ale ________ _________ _______ ______ signals. wrl and wrh, and bhe and wr can be switched using software control. ________ ________ _____ n wrl, wrh, and rd selected with a 16-bit external data bus, data is written to even addresses ________ when the wrl signal is l and to the odd addresses when the ________ _____ wrh signal is l. data is read when rd is l. ______ _______ _____ n wr, bhe, and rd selected ______ _____ data is written when wr is l. data is read when rd is l. odd _______ addresses are accessed when bhe is l. use this mode when using an 8-bit external data bus. __________ while the input level at the hold pin is l, the microcomputer is __________ placed in the hold state. while in the hold state, hlda outputs a l level. ale is used to latch the address. while the input level of _______ the rdy pin is l, the microcomputer is in the ready state. this is an 8-bit i/o port equivalent to p0. pins in this port also function as uart0 and uart1 i/o pins as selected by software. this is an 8-bit i/o port equivalent to p0 (p7 0 and p7 1 are n channel open-drain output). pins in this port also function as timer a 0 Ca 3 , timer b5 or uart2 i/o pins as selected by software. p8 0 to p8 4 , p8 6 and p8 7 are i/o ports with the same functions as p0. using software, they can be made to function as the i/o pins for timer a4 and the input pins for external interrupts. p8 6 and p8 7 can be set using software to function as the i/o pins for a sub clock generation circuit. in this case, connect a quartz oscillator between p8 6 (x cout pin) and p8 7 (x cin pin). p8 5 is an input-only port that _______ _______ also functions for nmi. the nmi interrupt is generated when the _______ input at this pin changes from h to l. the nmi function cannot be cancelled using software. the pull-up cannot be set for this pin. this is an 8-bit i/o port equivalent to p0. pins in this port also function as si/o 3, 4 i/o pins, timer b0Cb4 input pins, d-a converter output pins, a-d converter extended input pins, or a-d trigger input pins as selected by software. this is an 8-bit i/o port equivalent to p0. pins in this port also funciton as a-d converter input pins. furthermore, p10 4 Cp10 7 also function as input pins for the key input interrupt function. note 1: in m30623(80-pin package), the following signals do not have the corresponding external pin. _______ _______ l p1 0 /d 8 to p1 4 /d 12 , p1 5 /d 13 /int 3 to p1 7 /d 15 /int 5 _______ _______ l p4 4 /cs0 to p4 7 /cs3 ________ ________ __ ___ l p7 2 /clk 2 /ta1 out /v, p7 3 /cst 2 /rts 2 /ta1 in /v, p7 4 /ta2 out /w, p7 5 /ta2 in /w l p9 1 /tb1 in /s in3 note 2: the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes.
11 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development memory operation of functional blocks the m16c/62t group accommodates certain units in a single chip. these units include rom and ram to store instructions and data and the central processing unit (cpu) to execute arithmetic/logic operations. also included are peripheral units such as timers, serial i/o, d-a converter, dmac, crc calculation circuit, a-d converter, and i/o ports. the following explains each unit. memory figure 1.4.1 is a memory map of the m16c/62t group. the address space extends the 1m bytes from address 00000 16 to fffff 16 . internal rom is located as the following, in m30623m4t-xxxgp from address f8000 16 to fffff 16 (32k bytes), in m30622m8t/m8v-xxxfp and m30623m8t/m8v-xxxgp from address f0000 16 to fffff 16 (64k bytes), in m30622mct/mcv-xxxfp and m30623mct/mcv-xxxgp from address e0000 16 to fffff 16 (128k bytes). _______ the vector table for fixed interrupts such as the reset and nmi are mapped to fffdc 16 to fffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. internal ram is located as the following, in m30623m4t-xxxgp from address 00400 16 to 00fff 16 (3k bytes), in m30622m8t/m8v-xxxfp and m30623m8t/m8v-xxxgp from address 00400 16 to 013ff 16 (4k bytes), in m30622mct/mcv-xxxfp and m30623mct/mcv-xxxgp from address 00400 16 to 017ff 16 (5k bytes). in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated. the sfr area is mapped to 00000 16 to 003ff 16 . this area accommodates the control registers for peripheral devices such as i/o ports, a-d converter, serial i/o, and timers, etc. figures 1.7.1 to 1.7.3 are location of peripheral unit control registers. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is mapped to ffe00 16 to fffdb 16 . if the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. in memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. for example, in the m30623mct/mcv-xxxgp, the following spaces cannot be used. ? the space between 01000 16 and 03fff 16 (memory expansion and microprocessor modes) ? the space between d0000 16 and d7fff 16 (memory expansion mode) but the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. figure 1.4.1. memory map sfr area for details, see figures 1.7.1 to 1.7.3 internal ram area external area internal ram area reset watchdog timer single step address match brk instruction overflow undefined instruction special page vector table 00000 16 00400 16 04000 16 fffff 16 fffdc 16 ffe00 16 dbc nmi fffff 16 xxxxx 16 yyyyy 16 d0000 16 type no. xxxxx 16 yyyyy 16 m30623m4t-xxxgp m30622m8t/m8v-xxxfp m30623m8t/m8v-xxxgp m30622mct/mcv-xxxfp m30623mct/mcv-xxxgp 00fff 16 f8000 16 013ff 16 f0000 16 017ff 16 e0000 16 internal reserved area (note 1) internal reserved area (note 1) note 1. in memory expansion and microprocessor modes, can not be used. note 2. in memory expansion mode, can not be used. note 3. the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes.
12 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development cpu central processing unit (cpu) the cpu has a total of 13 registers shown in figure 1.5.1. seven of these registers (r0, r1, r2, r3, a0, a1, and fb) come in two sets; therefore, these have two register banks. (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, and r3) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h/r1h), and low-order bits as (r0l/r1l). in some instructions, registers r2 and r0, as well as r3 and r1 can use as 32-bit data registers (r2r0/r3r1). (2) address registers (a0 and a1) address registers (a0 and a1) are configured with 16 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). aaaaaaa aaaaaaa h l b15 b8 b7 b0 r0 (note) aaaaaaa h l b15 b8 b7 b0 r1 (note) r2 (note) aaaaaaa aaaaaaa b15 b0 r3 (note) aaaaaaa aaaaaaa b15 b0 a0 (note) aaaaaaa aaaaaaa b15 b0 a1 (note) aaaaaaa aaaaaaa b15 b0 fb (note) aaaaaaa b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 h l program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register pc intb usp isp sb flg note: these re g isters consist of two re g ister banks. a a aa aa aa aa a a aaaaaaa aaaaaaa a a aa aa aa aa aa aa a a c d z s b o i u ipl figure 1.5.1. central processing unit register
13 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development cpu (3) frame base register (fb) frame base register (fb) is configured with 16 bits, and is used for fb relative addressing. (4) program counter (pc) program counter (pc) is configured with 20 bits, indicating the address of an instruction to be executed. (5) interrupt table register (intb) interrupt table register (intb) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) stack pointer (usp/isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each config- ured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). (7) static base register (sb) static base register (sb) is configured with 16 bits, and is used for sb relative addressing. (8) flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure 1.5.2 shows the flag register (flg). the following explains the function of each flag: ? bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ? bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is 1, a single-step interrupt is generated after instruction execution. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 2: zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, cleared to 0. ? bit 3: sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, cleared to 0 . ? bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. ? bit 5: overflow flag (o flag) this flag is set to 1 when an arithmetic operation resulted in overflow; otherwise, cleared to 0. ? bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is 0, and is enabled when this flag is 1. this flag is cleared to 0 when the interrupt is acknowledged.
14 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development cpu ? bit 7: stack pointer select flag (u flag) interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1. this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software interrupt nos. 0 to 31 is executed. ? bits 8 to 11: reserved area ? bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. ? bit 15: reserved area the c, z, s, and o flags are changed when instructions are executed. see the software manual for details. figure 1.5.2. flag register (flg) carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level reserved area flag register (flg) aa aa aa aa a a aa aa aaaaaaa aaaaaaa aa aa aa aa aa aa a a aa aa c d z s b o i u ipl b0 b15
15 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer reset figure 1.6.2. reset sequence reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see software reset for details of software resets.) this section explains on hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level l (0.2v cc max.) for at least 20 cycles. when the reset pin level is then returned to the h level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. figure 1.6.1 shows the example reset circuit. figure 1.6.2 shows the reset sequence. figure 1.6.1. example reset circuit x in microprocessor mode byte = ? bclk ffffc 16 ffffd 16 ffffe 16 content of reset vector bclk 24 cycles more than 20 cycles are needed address ffffc 16 content of reset vector address ffffe 16 reset rd wr cs0 rd wr cs0 ffffc 16 content of reset vector address single chip mode ffffe 16 (?? microprocessor mode byte = ? (?? note 1: in m30623(80-pin package), the byte signal has no external pin, and is internally connected to the cnv ss signal. accordingly, in the microprocessor mode, byte = cnv ss = vcc. note 2: m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. note 3: m30623(80-pin package) is not provided with the chip select signals (cs0 to cs3). vcc reset 4.0v 0.8v 0v 5v 0v 5v vcc reset example when vcc=5v. more than 20 cycles of x in are needed.
16 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer reset ____________ table 1.6.1 shows the statuses of the other pins while the reset pin level is l. figures 1.6.3 and 1.6.4 show the internal status of the microcomputer immediately after the reset is cancelled. ____________ table 1.6.1. pin status when reset pin level is l status cnv ss = v cc cnv ss = v ss byte = v ss (note 1) byte = v cc pin name p0 p1 p2, p3, p4 0 to p4 3 p4 4 p4 5 to p4 7 p5 0 p5 1 p5 2 p5 3 p5 4 p5 5 p5 6 p5 7 p6, p7, p8 0 to p8 4 , p8 6 , p8 7 , p9, p10 input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) (pull-up resistor is on) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) data input (floating) data input (floating) address output (undefined) bclk output ale output (??level is output) cs0 output (??level is output) wr output (??level is output) rd output (??level is output) rdy input (floating) input port (floating) bclk output bhe output (undefined) hlda output (the output value depends on the input to the hold pin) hold input (floating) data input (floating) address output (undefined) cs0 output (??level is output) input port (floating) (pull-up resistor is on) input port (floating) input port (floating) rdy input (floating) ale output (??level is output) hold input (floating) hlda output (the output value depends on the input to the hold pin) rd output (??level is output) bhe output (undefined) wr output (??level is output) input port (floating) (pull-up resistor is on) note 1: in m30623(80-pin package), the byte signal has no external pin, and is internally connected to the cnv ss signal. accordingly, in the microprocessor mode, byte = cnv ss = v cc . note 2: in m30623(80-pin package), port p1, p4 4 to p4 7 , p7 2 to p7 5 and p9 1 have no external pin, and are internally the above conditions. after reset, set these ports to one of the following conditions. ?be output mode, and output ??level. ?pull-up resister is on.
17 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer reset figure 1.6.3. device's internal status after a reset is cleared (8) (9) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (1) (0004 16 ) processor mode register 0 (note 1) (2) (0005 16 ) processor mode register 1 (4) (0007 16 ) system clock control register 1 (5) (0008 16 ) chip select control register (6) (0009 16 ) address match interrupt enable register (7) protect register (3) (0006 16 ) system clock control register 0 00 16 (000a 16 ) (000f 16 ) watchdog timer control register (0010 16 ) address match interrupt register 0 (0011 16 ) (0012 16 ) (0014 16 ) address match interrupt register 1 (0015 16 ) (0016 16 ) (002c 16 ) dma0 control register (003c 16 ) dma1 control register (004a 16 ) bus collision detection interrupt (004b 16 ) dma0 interrupt control register (004c 16 ) dma1 interrupt control register (004d 16 ) key input interrupt control register (24) a-d conversion interrupt control register (004e 16 ) data bank register (000b 16 ) (10) (0044 16 ) int3 interrupt control register (0045 16 ) timer b5 interrupt control register (0046 16 ) timer b4 interrupt control register (0047 16 ) timer b3 interrupt control register (0048 16 ) si/o4 interrupt control register (0049 16 ) si/o3 interrupt control register (25) (26) (27) (28) (29) (30) (004f 16 ) uart2 transmit interrupt control register (0050 16 ) uart2 receive interrupt control register (0051 16 ) uart0 transmit interrupt control register (0052 16 ) uart0 receive interrupt control register (0053 16 ) uart1 transmit interrupt control register (0054 16 ) uart1 receive interrupt control register (31) (32) (33) (34) (39) (41) (40) (35) (36) (37) (38) (0055 16 ) timer a0 interrupt control register (0056 16 ) timer a1 interrupt control register (0057 16 ) timer a2 interrupt control register (0058 16 ) timer a3 interrupt control register (0059 16 ) timer a4 interrupt control register (005a 16 ) timer b0 interrupt control register (005b 16 ) timer b1 interrupt control register (005c 16 ) timer b2 interrupt control register (005d 16 ) int0 interrupt control register (005e 16 ) int1 interrupt control register (005f 16 ) int2 interrupt control register (45) (46) (0348 16 ) three-phase pwm control register 0 (0349 16 ) three-phase pwm control register 1 (034a 16 ) three-phase output buffer register 0 (034b 16 ) three-phase output buffer register 1 (43) (42) (0340 16 ) timer b3,4,5 count start flag (44) (47) (035b 16 ) timer b3 mode register (48) (035c 16 ) timer b4 mode register (49) (035d 16 ) timer b5 mode register (50) (035f 16 ) interrupt cause select register 0 00 0 0 0 01 0 0 100 1 00 0 0 000 0 00 0 1 000 00 00 0 00 16 ? \ 00 ? ?? ? 00 16 00 16 00 0 0 00 16 00 16 00 0 0 0 00 0 0 0?0 0 00 0 0 0?0 00 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 00 0 ?0 0 00 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 00 0 ?0 0 00 0 ?0 0 00 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 0 ?0 0 00 16 00 16 00 16 00 16 00 16 0 ?0 0 0 00 0 ?0 0 0 00 0 ?0 0 0 00 0 0 0 0 note 1 : when the v cc level is applied to the cnv ss pin , it is 03 16 at a reset. control register \ : this bit is the cold start / warm start flag, is set to ??at power on reset (refer to page 71). 5 : nothing is mapped to this bit. ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set.
18 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer reset figure 1.6.4. device's internal status after a reset is cleared (03e2 16 ) port p0 direction register (80) (03e3 16 ) port p1 direction register (81) (03e6 16 ) port p2 direction register (82) (03e7 16 ) port p3 direction register (83) (03ea 16 ) port p4 direction register (84) (03eb 16 ) port p5 direction register (85) (03ee 16 ) port p6 direction register (86) (03ef 16 ) port p7 direction register (87) (03f2 16 ) port p8 direction register (88) (03f3 16 ) port p9 direction register (89) (03f6 16 ) port p10 direction register (90) (03fc 16 ) pull-up control register 0 (91) (03fd 16 ) pull-up control register 1 (note 1) (92) (03fe 16 ) pull-up control register 2 (93) data registers (r0/r1/r2/r3) (94) frame base register (fb) (96) address registers(a0/a1) (95) interrupt table register (intb) (97) user stack pointer (usp) (98) interrupt stack pointer (isp) (99) static base register (sb) (100) flag register(flg) (101) (03dc 16 ) d-a control register (79) (0383 16 ) trigger select flag (0384 16 ) up-down flag (58) (57) (0396 16 ) timer a0 mode register (59) (0397 16 ) timer a1 mode register (60) (0398 16 ) timer a2 mode register (63) (039b 16 ) timer b0 mode register (64) (039c 16 ) timer b1 mode register (65) (039d 16 ) timer b2 mode register (66) (61) (0399 16 ) timer a3 mode register (62) (039a 16 ) timer a4 mode register (0382 16 ) one-shot start flag (56) (03a8 16 ) uart1 transmit/receive mode register (70) (03ac 16 ) uart1 transmit/receive control register 0 (71) (03ad 16 ) uart1 transmit/receive control register 1 (72) (03b0 16 ) uart transmit/receive control register 2 (73) (03b8 16 ) dma0 cause select register (74) (03ba 16 ) dma1 cause select register (75) (03a0 16 ) uart0 transmit/receive mode register (67) (03a4 16 ) uart0 transmit/receive control register 0 (68) (03a5 16 ) uart0 transmit/receive control register 1 (69) (03d4 16 ) a-d control register 2 (76) (03d6 16 ) a-d control register 0 (77) (03d7 16 ) a-d control register 1 (78) uart2 transmit/receive control register 1 uart2 transmit/receive control register 0 count start flag (0378 16 ) (037d 16 ) (037c 16 ) (0380 16 ) 00 16 (0381 16 ) clock prescaler reset flag (53) (54) uart2 transmit/receive mode register (51) (52) (55) 0000 0 00 00 0010 100 00 16 0 0000 00 0 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 0 ?000 00 0 ?000 00 0 ?000 00 00 16 1000 0000 0010 0000 1000 0000 0010 0000 00 16 00 16 000 00 00 0 00 0 00 16 0? 00 00 ? ? 00 16 00 16 00 16 00 16 00 16 00 16 00 16 0000 00 00 16 00 16 0 00 16 00 16 00 16 00 16 00 16 0000 16 0000 16 0000 16 0000 16 0000 16 0000 16 0000 16 0000 16 (102) (103) (104) (105) (03ff 16 ) port control register 00 16 si/o3 control register (0362 16 )0100 0 000 si/o4 control register (0366 16 )0100 0 000 (0377 16 ) 00 16 uart2 special mode register 0 note 1 : when the v cc level is applied to the cnv ss pin, it is 02 16 at a reset. the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. 5 : nothing is mapped to this bit. ? : undefined
19 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer sfr figure 1.7.1. location of peripheral unit control registers (1) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 032a 16 032b 16 032c 16 032d 16 032e 16 032f 16 0330 16 0331 16 0332 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 033f 16 dma0 control register (dm0con) dma0 source pointer (sar0) dma0 transfer counter (tcr0) dma1 control register (dm1con) dma1 source pointer (sar1) dma1 transfer counter (tcr1) dma1 destination pointer (dar1) watchdog timer start register (wdts) watchdog timer control register (wdc) processor mode register 0 (pm0) address match interrupt register 0 (rmad0) address match interrupt register 1 (rmad1) chip select control register (csr) system clock control register 0 (cm0) system clock control register 1 (cm1) address match interrupt enable register (aier) protect register (prcr) processor mode register 1(pm1) data bank register (dbr) dma0 destination pointer (dar0) timer a1 interrupt control register (ta1ic) uart0 transmit interrupt control register (s0tic) timer a0 interrupt control register (ta0ic) timer a2 interrupt control register (ta2ic) uart0 receive interrupt control register (s0ric) uart1 transmit interrupt control register (s1tic) uart1 receive interrupt control register (s1ric) dma1 interrupt control register (dm1ic) dma0 interrupt control register (dm0ic) key input interrupt control register (kupic) a-d conversion interrupt control register (adic) bus collision detection interrupt control register (bcnic) uart2 transmit interrupt control register (s2tic) uart2 receive interrupt control register (s2ric) int1 interrupt control register (int1ic) timer b0 interrupt control register (tb0ic) timer b2 interrupt control register (tb2ic) timer a3 interrupt control register (ta3ic) int2 interrupt control register (int2ic) int0 interrupt control register (int0ic) timer b1 interrupt control register (tb1ic) timer a4 interrupt control register (ta4ic) int3 interrupt control register (int3ic) timer b5 interrupt control register (tb5ic) timer b4 interrupt control register (tb4ic) timer b3 interrupt control register (tb3ic) si/o4 interrupt control register (s4ic) int5 interrupt control register (int5ic) si/o3 interrupt control register (s3ic) int4 interrupt control register (int4ic)
20 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer sfr figure 1.7.2. location of peripheral unit control registers (2) 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 timer a1-1 register (ta11) timer a2-1 register (ta21) dead time timer(dtt) timer b2 interrupt occurrence frequency set counter(ictb2) three-phase pwm control register 0(invc0) three-phase pwm control register 1(invc1) three-phase output buffer register 0(idb0) three-phase output buffer register 1(idb1) timer b3 register (tb3) timer b4 register (tb4) timer b5 register (tb5) timer b3, 4, 5 count start flag (tbsr) timer b3 mode register (tb3mr) timer b4 mode register (tb4mr) timer b5 mode register (tb5mr) interrupt cause select register (ifsr) timer a0 (ta0) timer a1 (ta1) timer a2 (ta2) timer b0 (tb0) timer b1 (tb1) timer b2 (tb2) count start flag (tabsr) one-shot start flag (onsf) timer a0 mode register (ta0mr) timer a1 mode register (ta1mr) timer a2 mode register (ta2mr) timer b0 mode register (tb0mr) timer b1 mode register (tb1mr) timer b2 mode register (tb2mr) up-down flag (udf) timer a3 (ta3) timer a4 (ta4) timer a3 mode register (ta3mr) timer a4 mode register (ta4mr) trigger select register (trgsr) clock prescaler reset flag (cpsrf) uart0 transmit/receive mode register (u0mr) uart0 transmit buffer register (u0tb) uart0 receive buffer register (u0rb) uart1 transmit/receive mode register (u1mr) uart1 transmit buffer register (u1tb) uart1 receive buffer register (u1rb) uart0 bit rate generator (u0brg) uart0 transmit/receive control register 0 (u0c0) uart0 transmit/receive control register 1 (u0c1) uart1 bit rate generator (u1brg) uart1 transmit/receive control register 0 (u1c0) uart1 transmit/receive control register 1 (u1c1) dma1 request cause select register (dm1sl) dma0 request cause select register (dm0sl) crc data register (crcd) crc input register (crcin) si/o3 transmit/receive register (s3trr) si/o4 transmit/receive register (s4trr) si/o3 control register (s3c) si/o3 bit rate generator (s3brg) si/o4 bit rate generator (s4brg) si/o4 control register (s4c) uart2 special mode register (u2smr) uart2 receive buffer register (u2rb) uart2 transmit buffer register (u2tb) uart2 transmit/receive control register 0 (u2c0) uart2 transmit/receive mode register (u2mr) uart2 transmit/receive control register 1 (u2c1) uart2 bit rate generator (u2brg) uart transmit/receive control register 2 (ucon) timer a4-1 register (ta41)
21 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer sfr figure 1.7.3. location of peripheral unit control registers (3) 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 a-d register 7 (ad7) a-d register 0 (ad0) a-d register 1 (ad1) a-d register 2 (ad2) a-d register 3 (ad3) a-d register 4 (ad4) a-d register 5 (ad5) a-d register 6 (ad6) port p0 (p0) port p0 direction register (pd0) port p1 (p1) port p1 direction register (pd1) port p2 (p2) port p2 direction register (pd2) port p3 (p3) port p3 direction register (pd3) port p4 (p4) port p4 direction register (pd4) port p5 (p5) port p5 direction register (pd5) port p6 (p6) port p6 direction register (pd6) port p7 (p7) port p7 direction register (pd7) port p8 (p8) port p8 direction register (pd8) port p9 (p9) port p9 direction register (pd9) port p10 (p10) port p10 direction register (pd10) pull-up control register 0 (pur0) pull-up control register 1 (pur1) pull-up control register 2 (pur2) a-d control register 0 (adcon0) a-d control register 1 (adcon1) d-a register 0 (da0) d-a register 1 (da1) d-a control register (dacon) a-d control register 2 (adcon2) port control register (pcr)
22 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development memory space expansion functions memory space expansion features here follows the description of the memory space expansion function. with the processor running in memory expansion mode or in microprocessor mode, the memory space expansion features provide the means of expanding the accessible space. the memory space expansion features run in one of the three modes given below. (1) normal mode (no expansion) (2) memory space expansion mode 1 (to be referred as expansion mode 1) (3) memory space expansion mode 2 (to be referred as expansion mode 2) use bits 5 and 4 (pm15, pm14) of processor mode register 1 to select a desired mode. the external memory area the chip select signal indicates is different in each mode so that the accessible memory space varies. table 1.8.1 shows how to set individual modes and corresponding accessible memory spaces. for external memory area the chip select signal indicates, see table 1.12.1 on page 33. but m30623 (80-pin package) is not provided with the output pin for the chip select signal. and, the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. table 1.8.1. the way of setting memory space expansion modes and corresponding memory spaces expansion mode how to set pm15 and pm14 accessible memory space normal mode (no expansion) 0, 0 up to 1m byte expansion mode 1 1, 0 up to 1.2m bytes expansion mode 2 1, 1 up to 4m bytes here follows the description of individual modes. (1) normal mode (a mode with memory not expanded) normal mode means a mode in which memory is not expanded. figure 1.8.1 shows the memory maps and the chip select areas in normal mode. figure 1.8.1. the memory maps and the chip select areas in normal mode microprocessor mode aaaa aaaa aaaa aaaa aaaa aaaa aaaa sfr area internal ramarea external area internal area reserved 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 d0000 16 08000 16 memory expansion mode aaaaa aaaaa aaaaa aaaaa aaaaa sfr area internal ram area external area internal rom area internal area reserved internal area reserved cs3 (16k bytes) cs2 (128k bytes) cs1 (32k bytes) cs0 memory expansion mode: 640k bytes microprocessor mode: 832k bytes 28000 16 30000 16 04000 16 normal mode (memory area = 1m bytes for pm15 = 0, pm14 = 0) type no. xxxxx 16 yyyyy 16 m30623m4t-xxxgp m30622m8t/m8v-xxxfp m30623m8t/m8v-xxxgp m30622mct/mcv-xxxfp m30623mct/mcv-xxxgp 00fff 16 f8000 16 013ff 16 f0000 16 017ff 16 e0000 16 note 1. m30623(80-pin package) is not provided with the output pins for chip select signals. note 2. the m16c/62t group is not guaranteed to operatein memory expansion and microprocessor modes. note 3. the memory maps in single-chip mode are omitted.
23 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development memory space expansion functions (2) expansion mode 1 in this mode, the memory space can be expanded by 176k bytes in addition to that in normal mode. figure 1.8.2 shows the memory location and chip select area in expansion mode 1. _______ _______ _______ in accessing data in expansion mode 1, cs3, cs2, and cs1 go active in the area from 04000 16 through _______ 2ffff 16 ; in fetching a program, cs0 goes active. that is, the address space is expanded by using the ________ _______ _______ area from 04000 16 through 2ffff 16 (176k bytes) appropriately for accessing data (cs3, cs2, cs1) _______ and fetching a program (cs0). figure 1.8.2. memory location and chip select area in expansion mode 1 microprocessor mode sfr area internal ram area external area internal area reserved 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 d0000 16 08000 16 memory expansion mode aaaa aaaa aaaa aaaa aaaa sfr area internal ram area external area internal rom area internal area reserved internal area reserved cs3 (16k bytes) cs2 (128 kbytes) cs1 (32k bytes) 28000 16 30000 16 04000 16 expansion mode 1 (memory space = 1.2m bytes for pm15 = 1, pm14 = 0) cs0 memory expansion mode: 816k bytes microprocessor mode: 1008k bytes 04000 16 to 2ffff 16 30000 16 to fffff 16 176k bytes = the extent of memory expanded cs0:active both in fetching a program and in accessing data cs0:active in fetching a program cs1, cs2, cs3:active in accessing data type no. xxxxx 16 yyyyy 16 m30623m4t-xxxgp m30622m8t/m8v-xxxfp m30623m8t/m8v-xxxgp m30622mct/mcv-xxxfp m30623mct/mcv-xxxgp 00fff 16 f8000 16 013ff 16 f0000 16 017ff 16 e0000 16 note 1. m30623(80-pin package) is not provided with the output pin for the chip select signal. note 2. the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. note 3. the memory maps in single-chip mode are omitted.
24 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development memory space expansion functions an example of connecting the mcu with external memories in expansion mode 1 (an example of using m30622mc in microprocessor mode) aaaa a aa a a aa a aaaa aaaa a aa a a aa a a aa a aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa sfr area internal ram area external area internal area reserved 00000 16 00400 16 017ff 16 fffff 16 d0000 16 08000 16 cs2 (128k bytes) 28000 16 30000 16 04000 16 cs0 sram (128k bytes) flash rom (1m byte) usable for programs only usable both for programs and for data (1008k bytes) usable for data only 17 8 m30622mc d0 to d7 a0 to a16 a17 a19 rd wr cs1 cs2 cs3 cs0 a18 1m byte flash rom d0 to d7 a0 to a16 a17 a18 a19 oe cs 128k bytes sram dq0 to dq7 a0 to a16 s2 w oe s1 note 1. m30623(80-pin package) is not provided with the output pin for the chip select signal. note 2. the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. a connection example figure 1.8.3 shows a connection example of the mcu with the external memories in expansion mode 1. _______ _______ in this example, cs0 is connected with a 1-m byte flash rom and cs2 is connected with a 128-k byte sram. figure 1.8.3. external memory connect example in expansion mode 1
25 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development memory space expansion functions (3) expansion mode 2 in expansion mode 2, the data bank register (0000b 16 ) goes effective. figure 1.8.4 shows the data bank register. figure 1.8.4. data bank register data bank register symbol address when reset dbr 000b 16 00 16 bit name description bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ofs offset bit 0: not offset 1: offset bsr bank selection bits 0 0 0: bank 0 0 0 1: bank 1 0 1 0: bank 2 0 1 1: bank 3 1 0 0: bank 4 1 0 1: bank 5 1 1 0: bank 6 1 1 1: bank 7 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? b5 b4 b3 b5 b4 b3 microprocessor mode aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa aaaaa sfr area internal ram area external area internal area reserved 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 d0000 16 08000 16 memory expansion mode aaaa aaaa aaaa aaaa aaaa aaaa sfr are a internal ram area external area internal rom area internal area reserved internal area reserved cs3 (16k bytes) cs2 (128k bytes) cs1 (96k bytes) 28000 16 40000 16 04000 16 expansion mode 2 (memory space = 4m bytes for pm15 = 1, pm14 = 1) cs0 addresses from 40000 16 through bffff 16 bank 7 in fetching a program a bank selected by use of the bank selection bits in accessing data addresses from c0000 16 through fffff 16 bank 7 invariably bank number is output to cs3 to cs1 memory expansion mode: 512k bytes x 7banks + 256k bytes microprocessor mode: 512k bytes x 8banks type no. xxxxx 16 yyyyy 16 m30623m4t-xxxgp m30622m8t/m8v-xxxfp m30623m8t/m8v-xxxgp m30622mct/mcv-xxxfp m30623mct/mcv-xxxgp 00fff 16 f8000 16 013ff 16 f0000 16 017ff 16 e0000 16 note 1. m30623(80-pin package) is not provided with the output pin for the chip select signal. note 2. the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. note 3. the memory maps in single-chip mode are omitted. figure 1.8.5. memory location and chip select area in expansion mode 2
26 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development memory space expansion functions the data bank register is made up of the bank selection bits (bits 5 through 3) and the offset bit (bit 2). the bank selection bits are used to set a bank number for accessing data lying between 40000 16 and bffff 16 . assigning 1 to the offset bit provides the means to set offsets covering 40000 16 . figure 1.8.5 shows the memory location and chip select areas in expansion mode 2. _______ the area relevant to cs0 ranges from 40000 16 through fffff 16 . as for the area from 40000 16 through _______ bffff 16 , the bank number set by use of the bank selection bits are output from the output terminals cs3 _______ _______ _______ - cs1 only in accessing data. in fetching a program, bank 7 (111 2 ) is output from cs3 - cs1. as for the _______ _______ area from c0000 16 through fffff 16 , bank 7 (111 2 ) is output from cs3 - cs1 without regard to accessing data or to fetching a program. _______ _______ _______ in accessing an area irrelevant to cs0, a chip select signal cs3 (4000 16 - 7fff 16 ), cs2 (8000 16 - _______ 27fff 16 ), and cs1 (28000 16 - 3ffff 16 ) is output depending on the address as in the past. figure 1.8.6 shows an example of connecting the mcu with a 4-m byte rom and to a 128-k byte sram. _______ _______ _______ _______ connect the chip select of 4-m byte rom with cs0. connect m16cs cs3, cs2, and cs1 with address inputs a21, a20, and a19 respectively. connect m16cs output a19 with address input a18. figure 1.8.7 shows the relationship between addresses of the 4-m byte rom and those of m16c. an example of connecting the mcu with external memories in expansion mode 2 (m30622mc, microprocessor mode) 17 8 m30622mct-xxxfp d0 to d7 a0 to a16 a17 rd wr cs1 cs2 cs3 cs0 a19 4-m byte rom d0 to d7 a0 to a16 a17 a18 a19 oe cs 128-k byte sram dq0 to dq7 a0 to a16 s2 w oe s1 a20 a21 note 1. if only one chip select terminal (s1 or s2) is present, decoding by use of an external circuit is required. note 2. m30623(80-pin package) is not provided with the output pin for the chip select signal. note 3. the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. with no offsets effected, banks switch from one 512-k byte segment to another 512-k byte segment. bank selection bits need to be changed in dealing with data lying across the boundary between banks every time a bank switches to another. assigning 1 to the offset bit brings about offsets covering 40000 16 so that data can be accessed without changing the bank selection bits. for instance, accessing 80000 16 of bank 0 with offsets ef- fected causes the output bank number to turn to 1, and ad19 is inverted to be out- put; this results in accessing 40000 16 of bank 1. on the other hand, the sram? chip select assumes _______ that cs0=1 (not selected) _______ and cs2=0 (selected), so _______ connect cs0 with s2 and _______ ____ cs2 with s1. if the sram doesn? have a bipolar chip select input terminal, decode _______ _______ cs0 and cs2 externally. figure 1.8.6. an example of connecting the mcu with external memories in expansion mode 2
27 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development memory space expansion functions 000000 080000 100000 180000 200000 280000 380000 3fffff rom address m16c address 40000 bffff 40000 bffff 3c0000 340000 2c0000 240000 1c0000 140000 0c0000 040000 bank 0 bank 1 40000 bffff 40000 bffff bank 1 bank 2 40000 bffff 40000 bffff bank 2 bank 3 40000 bffff 40000 bffff bank 3 bank 4 40000 bffff 40000 bffff bank 4 bank 5 40000 bffff 40000 bffff bank 5 bank 6 40000 bffff 40000 bffff bank 6 40000 bank 7 c0000 fffff 7ffff aaaa a aa a aaaa aaaa a aa a aaaa aaaa aaaa aaaa a aa a aaaa aaaa a aa a aaaa aaaa aaaa aaaa a aa a aaaa aaaa a aa a aaaa data area aaaa aaaa aaaa a aa a aaaa aaaa a aa a aaaa aaaa a aa a aaaa aaaa a aa a aaaa aaaa a aa a aaaa program/ data area areas used for data only 000000 16 to 380000 16 area commonly used for data and programs 380000 16 to 3bffff 16 area commonly used for data and programs 3c0000 16 to 3fffff 16 address area map of 4-m byte rom offset bit = 0 offset bit = 1 300000 program/ data area data area bank 0 figure 1.8.7. relationship between addresses on 4-m byte rom and those on m16c
28 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer software reset writing 1 to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software) reset to the microcomputer. a software reset has almost the same effect as a hardware reset. the contents of internal ram are preserved. software reset processor mode (1) types of processor mode one of three processor modes can be selected: single-chip mode, memory expansion mode, and micro- processor mode. the functions of some pins, the memory map, and the access space differ according to the selected processor mode. but m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. ? single-chip mode in single-chip mode, only internal memory space (sfr, internal ram, and internal rom) can be accessed. ports p0 to p10 can be used as programmable i/o ports or as i/o ports for the internal peripheral functions. ? memory expansion mode in memory expansion mode, external memory can be accessed in addition to the internal memory space (sfr, internal ram, and internal rom). in this mode, some of the pins function as the address bus, the data bus, and as control signals. the number of pins assigned to these functions depends on the bus and register settings. (see bus settings for details.) ? microprocessor mode in microprocessor mode, the sfr, internal ram, and external memory space can be accessed. the internal rom area cannot be accessed. in this mode, some of the pins function as the address bus, the data bus, and as control signals. the number of pins assigned to these functions depends on the bus and register settings. (see bus settings for details.) (2) setting processor modes the processor mode is set using the cnv ss pin and the processor mode bits (bits 1 and 0 at address 0004 16 ). do not set the processor mode bits to 10 2 . regardless of the level of the cnv ss pin, changing the processor mode bits selects the mode. therefore, never change the processor mode bits when changing the contents of other bits. also do not attempt to shift to or from the microprocessor mode within the program stored in the internal rom area. ? applying v ss to cnv ss pin the microcomputer begins operation in single-chip mode after being reset. memory expansion mode is selected by writing 01 2 to the processor mode is selected bits. ? applying v cc to cnv ss pin the microcomputer starts to operate in microprocessor mode after being reset. figure 1.9.1 shows the processor mode register 0 and 1. figure 1.10.1 shows the memory maps applicable for each of the modes when memory area dose not be expanded (normal mode).
mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer 29 processor mode figure 1.9.1. processor mode register 0 and 1 processor mode register 0 (note 1) symbol address when reset pm0 0004 16 00 16 (note 2) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0: single-chip mode 0 1: memory expansion mode 1 0: inhibited 1 1: microprocessor mode b1 b0 pm03 pm01 pm00 processor mode bit pm02 r/w mode select bit 0 : rd,bhe,wr 1 : rd,wrh,wrl software reset bit the device is reset when this bit is set to ?? the value of this bit is ??when read. pm04 0 0 : multiplexed bus is not used 0 1 : allocated to cs2 space 1 0 : allocated to cs1 space 1 1 : allocated to entire space (note4) b5 b4 multiplexed bus space select bit pm05 pm06 pm07 port p4 0 to p4 3 function select bit (note 3) 0 : address output 1 : port function (address is not output) bclk output disable bit 0 : bclk is output 1 : bclk is not output (pin is left floating) processor mode register 1 (note 1) symbol address when reset pm1 0005 16 00000xx0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. reserved bit must always be set to ? 0 a a a a a a a a a a a a a a a a a a a aa pm17 wait bit 0 : no wait state 1 : wait state inserted a aa a a aa aa a a aa aa memory area expansion bit (note 2) 0 0 : normal mode (do not expand) 0 1 : inhibited 1 0 : memory area expansion mode 1 1 1 : memory area expansion mode 2 b5 b4 pm15 pm14 aa reserved bit must always be set to 0 0 0 note 1: set bit 1 of the protect register (address 000a 16 ) to 1 when writing new values to this register. note 2: if the v cc voltage is applied to the cnv ss , the value of this register when reset is 03 16 . (pm00 and pm01 both are set to 1.) note 3: valid in microprocessor and memory expansion modes. note 4: if the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. the processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. the higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. note 5: the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. note 1: set bit 1 of the protect register (address 000a 16 ) to 1 when writing new values to this register. note 2: with the processor running in memory expansion mode or in microprocessor mode, setting this bit provides the means of expanding the external memory area. (normal mode: up to 1m byte, expansion mode 1: up to 1.2 m bytes, expansion mode 2: up to 4m bytes) for details, see memory space expansion functions. note 3: the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. reserved bit must always be set to 0 reserved bit must always be set to 0 a a
30 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer single-chip mode sfr area internal ram area inhibited internal rom area microprocessor mode sfr area internal ram area external area internally reserved area 00000 16 00400 16 xxxxx 16 yyyyy 16 fffff 16 d0000 16 external area : accessing this area allows the user to access a device connected externally to the microcomputer. 04000 16 memory expansion mode sfr area internal ram area external area internal rom area internally reserved area internally reserved area note: the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. type no. xxxxx 16 yyyyy 16 m30623m4t-xxxgp m30622m8t/m8v-xxxfp m30623m8t/m8v-xxxgp m30622mct/mcv-xxxfp m30623mct/mcv-xxxgp 00fff 16 f8000 16 013ff 16 f0000 16 017ff 16 e0000 16 processor mode figure 1.10.1. memory maps in each processor mode (without memeory area expansion, normal mode)
mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer 31 note 1: in m30623(80-pin package), the external data bus width cannot be switched (be fixed 8 bits). bus settings the byte pin and bits 4 to 6 of the processor mode register 0 (address 0004 16 ) are used to change the bus settings. in m30623(80-pin package), the byte signal has no external pin, and is internally connected to the cnv ss signal. accordingly, the external data bus width can be used only 8 bits. m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. table 1.11.1 shows the factors used to change the bus settings. (1) selecting external address bus width the address bus width for external output in the 1m bytes of address space can be set to 16 bits (64k bytes address space) or 20 bits (1m bytes address space). when bit 6 of the processor mode register 0 is set to 1, the external address bus width is set to 16 bits, and p2 and p3 become part of the address bus. p4 0 to p4 3 can be used as programmable i/o ports. when bit 6 of processor mode register 0 is set to 0, the external address bus width is set to 20 bits, and p2, p3, and p4 0 to p4 3 become part of the address bus. (2) selecting external data bus width the external data bus width can be set to 8 or 16 bits. (note, however, that only the separate bus can be set.) when the byte pin is l, the bus width is set to 16 bits; when h, it is set to 8 bits. (the internal bus width is permanently set to 16 bits.) while operating, fix the byte pin either to h or to l. (3) selecting separate/multiplex bus the bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. ? separate bus in this mode, the data and address are input and output separately. the data bus can be set using the byte pin to be 8 or 16 bits. when the byte pin is h, the data bus is set to 8 bits and p0 functions as the data bus and p1 as a programmable i/o port. when the byte pin is l, the data bus is set to 16 bits and p0 and p1 are both used for the data bus. when the separate bus is used for access, a software wait can be selected. ? multiplex bus in this mode, data and address i/o are time multiplexed. with an 8-bit data bus selected (byte pin = h), the 8 bits from d 0 to d 7 are multiplexed with a 0 to a 7 . with a 16-bit data bus selected (byte pin = l), the 8 bits from d 0 to d 7 are multiplexed with a 1 to a 8 . d 8 to d 15 are not multiplexed. in this case, the external devices connected to the multiplexed bus are mapped to the microcomputers even addresses (every 2nd address). to access these external de- vices, access the even addresses as bytes. the ale signal latches the address. it is output from p5 6 . before using the multiplex bus for access, be sure to insert a software wait. if the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. the processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. the higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. table 1.11.1. factors for switching bus settings bus settings bus setting switching factor switching external address bus width bit 6 of processor mode register 0 switching external data bus width byte pin switching between separate and multiplex bus bits 4 and 5 of processor mode register 0
32 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer bus settings table 1.11.2. pin functions for each processor mode i/o port i/o port i/o port i/o port processor mode memory expansion / microprocessor modes (separate bus) ?1? ?0 ?0 ?1?(note 2) 8 bits ? 16 bits ? 16 bits ? 8 bits ? 8 bits ? p0 0 to p0 7 p1 0 to p1 7 p2 0 p2 1 to p2 7 p3 0 p3 1 to p3 7 port p4 0 to p4 3 p4 0 to p4 3 function select bit = 1 port p4 0 to p4 3 p4 0 to p4 3 function select bit = 0 p5 0 to p5 3 p5 4 p5 5 p5 6 p5 7 p4 4 to p4 7 data bus data bus data bus data bus i/o port i/o port data bus i/o port data bus i/o port i/o port address bus address bus address bus i/o port address bus address bus i/o port address bus address bus address bus a 8 /d 7 i/o port address bus address bus address bus address bus i/o port i/o port i/o port i/o port i/o port i/o port address bus address bus address bus address bus i/o port i/o port i/o port i/o port i/o port i/o port i/o port ale single-chip mode multiplexed bus for the entire space memory expansion mode (note 1) address bus /data bus address bus /data bus address bus/ data bus (note 3) address bus/ data bus (note 3) address bus/ data bus (note 3) address bus/ data bus (note 3) either cs1 or cs2 is for multiplexed bus and others are for separate bus multiplexed bus space select bit data bus width byte pin level rdy hold hlda ale rdy hold hlda ale rdy hold hlda ale rdy hold hlda ale rdy hold hlda cs (chip select) or programmable i/o port (for details, refer to ?us control?) outputs rd, wrl, wrh, and bclk or rd, bhe, wr, and bclk (for details, refer to ?us control?) note 1: in m30623(80-pin package), set the data bus width to 8 bits by any of the following operations, to transfer the microcomputer to memory expansion mode correctly. ? at reset, input h to the cnv ss (byte) pin to start the program in microprocessor mode. then, set the processor mode bit to memory expansion mode. ? at reset, input l to the cnv ss (byte) pin to start the program in single-chip mode, and input h to this pin. then, set the processor mode bit to memory expansion mode. note 2: if the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. the processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. the higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select. note 3: address bus when in separate bus mode. note 4: in m30623(80-pin package), p1, p4 4 to p4 7 have no corresponding external pin. note 5: m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes.
mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer 33 bus control bus control the following explains the signals required for accessing external devices and software waits. the signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. the software waits are valid in all processor modes. m30623(80-pin package), in which the byte pin is connected to the cnv ss pin, and the external data bus width can be used 8 bits. m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. (1) address bus/data bus the address bus consists of the 20 pins a 0 to a 19 for accessing the 1m bytes of address space. the data bus consists of the pins for data i/o. when the byte pin is h, the 8 ports d 0 to d 7 function as the data bus. when byte is l, the 16 ports d 0 to d 15 function as the data bus. when a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed. (2) chip select signalin (in m30623(80-pin package), the chip select signals have no corresponding external pin.) the chip select signal is output using the same pins as p4 4 to p4 7 . bits 0 to 3 of the chip select control register (address 0008 16 ) set each pin to function as a port or to output the chip select signal. the chip select control register is valid in memory expansion mode and microprocessor mode. in single-chip mode, p4 4 to p4 7 function as programmable i/o ports regardless of the value in the chip select control register. _______ in microprocessor mode, only cs0 outputs the chip select signal after the reset state has been can- _______ _______ celled. cs1 to cs3 function as input ports. figure 1.12.1 shows the chip select control register. the chip select signal can be used to split the external area into as many as four blocks. tables 1.12.1 and 1.12.2 show the external memory areas specified using the chip select signal. memory space expansion mode specified address range normal mode (pm15,14=0,0) expansion mode 1 (pm15,14=1,0) expansion mode 2 (pm15,14=1,1) processor mode memory expansion mode microprocessor mode 30000 16 to fffff 16 (832k bytes) 04000 16 to cffff 16 (816k bytes) 04000 16 to fffff 16 (1008k bytes) 40000 16 to fffff 16 (512k bytes 5 8) 28000 16 to 2ffff 16 (32k bytes) 28000 16 to 3ffff 16 (96k bytes) 08000 16 to 27fff 16 (128k bytes) 04000 16 to 07fff 16 (16k bytes) chip select signal 40000 16 to bffff 16 (512k bytes 5 7 + 256k bytes) 30000 16 to cffff 16 (640k bytes) memory expansion mode microprocessor mode memory expansion mode microprocessor mode cs0 cs1 cs2 cs3 note 1: in m30623(80-pin package), the chip select signals have no corresponding external pin. note 2: the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. table 1.12.1. external areas specified by the chip select signals
34 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer bus control w function bit symbol bit name chip select control register symbol address when reset csr 0008 16 01 16 r b7 b6 b5 b4 b3 b2 b1 b0 cs1 cs0 cs3 cs2 cs0 output enable bit cs1 output enable bit cs2 output enable bit cs3 output enable bit cs1w cs0w cs3w cs2w cs0 wait bit cs1 wait bit cs2 wait bit cs3 wait bit 0 : chip select output disabled (normal port pin) 1 : chip select output enabled 0 : wait state inserted 1 : no wait state a a a a a a a a a a a a a a a a a a a a note: in m30623(80-pin package), the chip select signals has no corresponding external pin. so, this register is invalid. figure 1.12.1. chip select control register (3) read/write signals with a 16-bit data bus (byte pin =l), bit 2 of the processor mode register 0 (address 0004 16 ) select the _____ ________ ______ _____ ________ _________ combinations of rd, bhe, and wr signals or rd, wrl, and wrh signals. with an 8-bit data bus (byte _____ ______ _______ pin = h), use the combination of rd, wr, and bhe signals. (set bit 2 of the processor mode register 0 (address 0004 16 ) to 0.) tables 1.12.2 and 1.12.3 show the operation of these signals. _____ ______ ________ after a reset has been cancelled, the combination of rd, wr, and bhe signals is automatically selected. _____ _________ _________ when switching to the rd, wrl, and wrh combination, do not write to external memory until bit 2 of the processor mode register 0 (address 0004 16 ) has been set (note 1). note 1: before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000a 16 ) to 1. _____ ______ ________ table 1.12.3. operation of rd, wr, and bhe signals status of external data bus rd bhe wr hll lhl hlh lhh write 1 byte of data to odd address read 1 byte of data from odd address write 1 byte of data to even address read 1 byte of data from even address data bus width a0 h h l l hll l lhl l hl h / l lh h / l 8-bit (byte = ?? write data to both even and odd addresses read data from both even and odd addresses write 1 byte of data read 1 byte of data 16-bit (byte = ?? not used not used status of external data bus read data write 1 byte of data to even address write 1 byte of data to odd address write data to both even and odd addresses wrh wrl rd data bus width 16-bit (byte = ?? h h h h l h l h h l l l _____ ________ _________ table 1.12.2. operation of rd, wrl, and wrh signals note 1: m30623(80-pin package) can operate only when byte = h.
mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer 35 bus control (4) ale signal the ale signal latches the address when accessing the multiplex bus space. latch the address when the ale signal falls. when byte pin = ? when byte pin = ? ale address data (note 1) address (note 2) d 0 /a 0 to d 7 /a 7 a 8 to a 19 ale address data (note 1) address d 0 /a 1 to d 7 /a 8 a 9 to a 19 address a 0 note 1: floating when reading. note 2: when multiplexed bus for the entire space is selected, these are i/o ports. note 3: in m30623 (80-pin package), p1 0 to p1 7 which are in common with d8 to d15 are available. so, m30623 (80-pin package) can operate only when byte pin = ??(the width of external data bus is 16-bit). figure 1.12.2. ale signal and address/data bus ________ (5) the rdy signal ________ rdy is a signal that facilitates access to an external device that requires long access time. as shown in ________ figure 1.12.3, if an l is being input to the rdy at the bclk falling edge, the bus turns to the wait state. if ________ an h is being input to the rdy pin at the bclk falling edge, the bus cancels the wait state. table 1.12.4 shows the state of the microcomputer with the bus in the wait state, and figure 1.12.3 shows an example in ____ ________ which the rd signal is prolonged by the rdy signal. ________ the rdy signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the ________ chip select control register (address 0008 16 ) are set to 0. the rdy signal is invalid when setting 1 to all ________ bits 4 to 7 of the chip select control register (address 0008 16 ), but the rdy pin should be treated as properly as in non-using. ________ note 1: the rdy signal cannot be received immediately prior to a software wait. _____ note 2: in m30623(80-pin package), cs signals have no corresponding external pin. table 1.12.4. microcomputer status in ready state (note 1) item status oscillation on ___ _____ r/w signal, address bus, data bus, cs ________ maintain status when rdy signal received __________ ale signal, hlda, programmable i/o ports internal peripheral circuits on
36 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer bus control _____ ________ figure 1.12.3. example of rd signal extended by rdy signal aaaaaa aaa bclk tsu (rdy - bclk ) rdy rd tsu (rdy - bclk ) aa aa : wait using rdy signal : wait using software bclk rdy rd cs i (i=0 to 3) (note) in an instance of separate bus in an instance of multiplexed bus accept timing of rdy signal accept timing of rdy signal note: in m30623(80-pin package), the cs i signal (i = 0 to 3) has no corresponding ext e cs i (i=0 to 3) (note) __________ hold > dmac > cpu (6) hold signal the hold signal is used to transfer the bus privileges from the cpu to the external circuits. inputting l to __________ the hold pin places the microcomputer in the hold state at the end of the current bus access. this status __________ __________ is maintained and l is output from the hlda pin as long as l is input to the hold pin. table 1.12.5 shows the microcomputer status in the hold state. __________ bus-using priorities are given to hold, dmac, and cpu in order of decreasing precedence. figure 1.12.4. bus-using priorities table 1.12.5. microcomputer status in hold state item status oscillation on ___ _____ _______ r/w signal, address bus, data bus, cs, bhe floating programmable i/o ports p0, p1, p2, p3, p4, p5 floating p6, p7, p8, p9, p10 m aintains status when hold signal is received __________ hlda output l internal peripheral circuits on (but watchdog timer stops) ale signal undefined ______ ______ note 1: in m30623(80-pin package), p1, p4 4 to p4 7 (cs0 to cs3) and p7 2 to p7 5 , p9 1 have no correspond- ing external pin, but are internally the above conditions.
mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer 37 bus control (8) bclk output the user can choose the bclk output by use of bit 7 of processor mode register 0 (0004 16 ) (note). when set to 1, the output floating. note: before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000a 16 ) to 1. (7) external bus status when the internal area is accessed table 1.12.6 shows the external bus status when the internal area is accessed. table 1.12.6. external bus status when the internal area is accessed item sfr accessed internal rom/ram accessed address bus address output maintain status before accessed address of external area data bus when read floating floating when write output data undefined rd, wr, wrl, wrh rd, wr, wrl, wrh output output "h" bhe bhe output maintain status before accessed status of external area cs output "h" output "h" ale output "l" output "l" _____ note 1: in m30623(80-pin package), cs signals have no corresponding external pin.
38 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer bus control (9) software wait a software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 16 ) (note) and bits 4 to 7 of the chip select control register (address 0008 16 ). a software wait is inserted in the internal rom/ram area and in the external memory area by setting the wait bit of the processor mode register 1. when set to 0, each bus cycle is executed in one bclk cycle. when set to 1, each bus cycle is executed in two or three bclk cycles. after the microcomputer has been reset, this bit defaults to 0. when set to 1, a wait is applied to all memory areas (two or three bclk cycles), regardless of the contents of bits 4 to 7 of the chip select control register. set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric character- istics. however, when the user is using the rdy signal, the relevant bit in the chip select control register's bits 4 to 7 must be set to 0. when the wait bit of the processor mode register 1 is 0, software waits can be set independently for each of the 4 areas selected using the chip select signal. bits 4 to 7 of the chip select control register _______ _______ correspond to chip selects cs0 to cs3. when one of these bits is set to 1, the bus cycle is executed in one bclk cycle. when set to 0, the bus cycle is executed in two or three bclk cycles. these bits default to 0 after the microcomputer has been reset. the sfr area is always accessed in two bclk cycles regardless of the setting of these control bits. also, insert a software wait if using the multiplex bus to access the external memory area. table 1.12.7 shows the software wait and bus cycles. figure 1.12.5 shows example bus timing when using software waits. note 1: before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000a 16 ) to 1. note 2: in m30623(80-pin package), the chip select signals have no corresponding external pin. table 1.12.7. software waits and bus cycles area bus status wait bit bits 4 to 7 of chip select control register bus cycle invalid 1 2 bclk cycles external memory area separate bus 0 1 1 bclk cycle separate bus 0 0 2 bclk cycles separate bus 1 0 (note) 2 bclk cycles multiplex bus 0 0 3 bclk cycles multiplex bus 1 3 bclk cycles 0 (note) sfr internal rom/ram 0 invalid 1 bclk cycle invalid invalid 2 bclk cycles note: when using the rdy signal, always set to ??
mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer 39 bus control figure 1.12.5. typical bus timings using software wait output input address address bus cycle < separate bus (with wait) > bclk read signal write signal data bus address bus chip select bclk read signal address bus/ data bus chip select address address address bus data output address address input ale bus cycle < multiplexed bus > write signal bclk read signal write signal address bus address address bus cycle < separate bus (no wait) > output data bus chip select input note 1: in m30623(80-pin package), the chip select signals have no corresponding external pin.
40 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock generating circuit figure 1.13.2. examples of sub clock table 1.13.1. main clock and sub clock generating circuits clock generating circuit the clock generating circuit contains two oscillator circuits that supply the operating clock sources to the cpu and internal peripheral units. example of oscillator circuit figure 1.13.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. figure 1.13.2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figures 1.13.1 and 1.13.2 vary with each oscillator used. use the values recommended by the manufacturer of your oscillator. figure 1.13.1. examples of main clock main clock generating circuit sub clock generating circuit use of clock ? cpus operating clock source ? cpus operating clock source ? internal peripheral units ? timer a/bs count clock operating clock source source usable oscillator ceramic or crystal oscillator crystal oscillator pins to connect oscillator x in , x out x cin , x cout oscillation stop/restart function available available oscillator status immediately after reset oscillating stopped other externally derived clock can be input microcomputer (built-in feedback resistor) x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. microcomputer (built-in feedback resistor) x cin x cout externally derived clock open vcc vss note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. microcomputer (built-in feedback resistor) x cin x cout (note) c cin c cout r cd
41 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock generating circuit clock control figure 1.13.3 shows the block diagram of the clock generating circuit. sub clock cm04 f c32 cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 wdci : bit i at address 000f 16 x cin cm10 ?? write signal 1/32 x cout q s r wait instruction x out main clock cm05 f c cm02 f 1 q s r nmi interrupt request level judgment output reset software reset f c cm07=0 cm07=1 f ad aaa aaa divider a d 1/2 1/2 1/2 1/2 cm06=0 cm17,cm16=00 cm06=0 cm17,cm16=01 cm06=0 cm17,cm16=10 cm06=1 cm06=0 cm17,cm16=11 d a details of divider x in f 8 f 32 c b b 1/2 c f 32 sio2 f 8 sio2 f 1 sio2 bclk figure 1.13.3. clock generating circuit
42 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock generating circuit the following paragraphs describes the clocks generated by the clock generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after a reset, the clock is divided by 8 to the bclk. the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). stopping the clock reduces the power dissipation. after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the x out pin can be reduced using the x in -x out drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the x out pin reduces the power dissipation. this bit defaults to 1 when shifting to stop mode and after a reset. (2) sub clock the sub clock is generated by the sub clock oscillation circuit. no sub clock is generated after a reset. after oscillation is started using the port xc select bit (bit 4 at address 0006 16 ), the sub clock can be selected as the bclk by using the system clock select bit (bit 7 at address 0006 16 ). however, be sure that the sub clock oscillation has fully stabilized before switching. after the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the x cout pin can be reduced using the x cin -x cout drive capacity select bit (bit 3 at address 0006 16 ). reducing the drive capacity of the x cout pin reduces the power dissipation. this bit changes to 1 when shifting to stop mode and at a reset. (3) bclk the bclk is the clock that drives the cpu, and is either the main clock or fc or is derived by dividing the main clock by 2, 4, 8, or 16. the bclk is derived by dividing the main clock by 8 after a reset. when shifting to stop mode, the main clock division select bit (bit 6 at 0006 16 ) is set to 1. (4) peripheral function clock ? f 1 , f 8 , f 32, f 1sio2, f 8sio2, f 32sio2 the clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. the peripheral function clock is stopped by stopping the main clock or by setting the wait peripheral function clock stop bit (bit 2 at 0006 16 ) to 1 and then executing a wait instruction. ? f ad this clock has the same frequency as the main clock and is used for a-d conversion. (5) f c32 this clock is derived by dividing the sub clock by 32. it is used for the timer a and timer b counts. (6) f c this clock has the same frequency as the sub clock. it is used for the bclk and for the watchdog timer.
43 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock generating circuit figure 1.13.4 shows the system clock control registers 0 and 1. figure 1.13.4. clock control registers 0 and 1 system clock control register 0 (note 1) symbol address when reset cm0 0006 16 48 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p5 7 0 1 : f c output 1 0 : f 8 output 1 1 : f 32 output b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 cm06 clock output function select bit wait peripheral function clock stop bit 0 : do not stop f 1 , f 8 , f 32 in wait mode 1 : stop f 1 , f 8 , f 32 in wait mode x cin -x cout drive capacity select bit (note 2) 0 : low 1 : high port x c select bit 0 : i/o port 1 : x cin -x cout generation main clock (x in -x out ) stop bit (note 4) (note 5) 0 : on 1 : off main clock division select bit 0 (note 2) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (note 6) 0 : x in , x out 1 : x cin , x cout note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: changes to ??when shiffing to stop mode. note 3: when entering power saving mode, main clock stops using this bit. when returning from stop mode and operating with x in , set this bit to ?? when main clock oscillation is operating by itself, set system clock select bit (cm07) to ??before setting this bit to ?? note 4: when inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. note 5: if this bit is set to ?? x out turns ?? the built-in feedback resistor remains on, so x in turns pulled up to x out (?? via the feedback resistor. note 6: set port xc select bit (cm04) to ??before writing to this bit. the both bits can not be written at the same time. system clock control register 1 (note 1) symbol address when reset cm1 0007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (note4) 0 : clock on 1 : all clocks off (stop mode) note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: changes to ??when shiffing to stop mode. note 3: can be selected when bit 6 of the system clock control register 0 (address 0006 16 ) is ?? if ?? division mode is fixed at 8. note 4: if this bit is set to ?? x out turns ?? and the built-in feedback resistor turns null. cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high w r w r cm16 cm17 reserved bit always set to ? reserved bit always set to ? main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 0 reserved bit always set to ? reserved bit always set to ? 0 0 a a aa aa a a aa aa a a aa aa a a aa aa a a aa aa a a aa aa a a aa aa a aa a aa a aa a aa a aa a aa a aa a a aa aa
44 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock generating circuit clock output in single-chip mode, the clock output function select bits (bits 0 and 1 at address 0006 16 ) enable f 8 , f 32 , or fc to be output from the p5 7 /clk out pin. when the wait peripheral function clock stop bit (bit 2 at address 0006 16 ) is set to 1, the output of f 8 and f 32 stops when a wait instruction is executed. stop mode writing 1 to the all-clock stop control bit (bit 0 at address 0007 16 ) stops all oscillation and the microcom- puter enters stop mode. in stop mode, the content of the internal ram is retained provided that v cc re- mains above 2v. because the oscillation , bclk, f 1 to f 32 , f 1sio2 to f 32sio2 , f c , f c32 , and f ad stops in stop mode, peripheral functions such as the a-d converter and watchdog timer do not function. however, timer a and timer b operate provided that the event counter mode is set to an external pulse, and uarti(i = 0 to 2) functions provided an external clock is selected. table 1.13.2 shows the status of the ports in stop mode. stop mode is cancelled by a hardware reset or interrupt. if an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. when shifting to stop mode, the main clock division select bit 0 (bit 6 at 0006 16 ) is set to 1. note 1: ______ ______ in m30623(80-pin package), cs0 to cs3 have no corresponding external pin, but are internally the above conditions. table 1.13.2. port status during stop mode pin memory expansion mode single-chip mode microprocessor mode _______ _______ address bus, data bus, cs0 to cs3 retains status before stop mode _____ ______ ________ ________ _________ rd, wr, bhe, wrl, wrh h __________ hlda, bclk h ale h port retains status before stop mode retains status before stop mode clk out when fc selected valid only in single-chip mode h when f 8 , f 32 selected valid only in single-chip mode retains status before stop mode
45 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development wait mode when a wait instruction is executed, the bclk stops and the microcomputer enters the wait mode. in this mode, oscillation continues but the bclk and watchdog timer stop. writing 1 to the wait peripheral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. table 1.13.3 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or interrupt. if an interrupt is used to cancel wait mode, the microcomputer restarts using as bclk, the clock that had been selected when the wait instruction was executed. wait mode table 1.13.3. port status during wait mode pin memory expansion mode single-chip mode microprocessor mode _______ _______ address bus, data bus, cs0 to cs3 retains status before wait mode _____ ______ ________ ________ _________ rd, wr, bhe, wrl, wrh h __________ hlda,bclk h ale h port retains status before wait mode retains status before wait mode clk out when f c selected valid only in single-chip mode does not stop when f 8 , f 32 selected valid only in single-chip mode does not stop when the wait peripheral function clock stop bit is 0. when the wait peripheral function clock stop bit is 1, the status immediately prior to en- tering wait mode is main- tained. note 1: ______ ______ in m30623(80-pin package), cs0 to cs3 have no corresponding external pin, but are internally the above conditions.
46 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development status transition of bclk power dissipation can be reduced and low-voltage operation achieved by changing the count source for bclk. table 1.13.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. after a reset, operation defaults to division by 8 mode. when shifting to stop mode, the main clock division select bit 0 (bit 6 at address 0006 16 ) is set to 1. the following shows the operational modes of bclk. (1) division by 2 mode the main clock is divided by 2 to obtain the bclk. (2) division by 4 mode the main clock is divided by 4 to obtain the bclk. (3) division by 8 mode the main clock is divided by 8 to obtain the bclk. note that oscillation of the main clock must have stabilized before transferring from this mode to another mode. (4) division by 16 mode the main clock is divided by 16 to obtain the bclk. (5) no-division mode the main clock is used as the bclk. (6) low-speed mode f c is used as the bclk. note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa. at least 2 to 3 seconds are required after the sub clock starts. therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) low power dissipation mode f c is the bclk and the main clock is stopped. status transition of bclk 0 1 0 0 0 invalid division by 2 mode 1 0 0 0 0 invalid division by 4 mode invalid invalid 0 1 0 invalid division by 8 mode 1 1 0 0 0 invalid division by 16 mode 0 0 0 0 0 invalid no-division mode invalid invalid 1 invalid 0 1 low-speed mode invalid invalid 1 invalid 1 1 low power dissipation mode cm17 cm16 cm07 cm06 cm05 cm04 operating mode of bclk table 1.13.4. operating modes dictated by settings of system clock control registers 0 and 1
47 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development power control the following is a description of the three available power control modes: modes power control is available in three modes. (a) normal operation mode ? high-speed mode divide-by-1 frequency of the main clock becomes the bclk. the cpu operates with the internal clock selected. each peripheral function operates according to its assigned clock. ? medium-speed mode divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the bclk. the cpu operates according to the internal clock selected. each peripheral function oper- ates according to its assigned clock. ? low-speed mode f c becomes the bclk. the cpu operates according to the fc clock. the fc clock is supplied by the secondary clock. each peripheral function operates according to its assigned clock. ? low power consumption mode the main clock operating in low-speed mode is stopped. the cpu operates according to the f c clock. the fc clock is supplied by the secondary clock. the only peripheral functions that operate are those with the sub-clock selected as the count source. (b) wait mode the cpu operation is stopped. the oscillators do not stop. (c) stop mode all oscillators stop. the cpu and all built-in peripheral functions stop. this mode, among the three modes listed here, is the most effective in decreasing power consumption. figure 1.13.5 is the state transition diagram of the above modes. power control
48 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development figure 1.13.5. state transition diagram of power control mode transition of stop mode, wait mode transition of normal mode reset medium-speed mode (divided-by-8 mode) interrupt cm10 = ? all oscillators stopped cpu operation stopped medium-speed mode (divided-by-8 mode) bclk : f(x in )/8 cm07 = ?? cm06 = ? low-speed mode high-speed mode main clock is oscillating sub clock is stopped main clock is oscillating sub clock is stopped main clock is stopped sub clock is oscillating main clock is oscillating sub clock is oscillating low power dissipation mode high-speed/medium- speed mode low-speed/low power dissipation mode normal mode stop mode stop mode stop mode all oscillators stopped all oscillators stopped wait mode wait mode wait mode cpu operation stopped cpu operation stopped interrupt wait instruction interrupt wait instruction interrupt wait instruction cm10 = ? interrupt interrupt cm10 = ? bclk : f(x in )/2 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-2 mode) bclk : f(x in )/16 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? bclk : f(x in )/8 medium-speed mode (divided-by-8 mode) cm07 = ? cm06 = ? high-speed mode bclk : f(x in )/2 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-2 mode) bclk : f(x in )/16 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? bclk : f(x cin ) cm07 = ? bclk : f(x cin ) cm07 = ? main clock is oscillating sub clock is oscillating cm07 = ? (note 1, 3) cm07 = ??(note 1) cm06 = ? cm04 = ? cm07 = ? (note 2) cm07 = ??(note 1) cm06 = ??(note 3) cm04 = ? cm07 = ??(note 2) cm05 = ?? cm05 = ? cm05 = ? cm04 = ? cm04 = ? cm06 = ? (notes 1,3) cm06 = ? cm04 = ? cm04 = ? (notes 1, 3) note 1: switch clock after oscillation of main clock is sufficiently stable. note 2: switch clock after oscillation of sub clock is sufficiently stable. note 3: change cm06 after changing cm17 and cm16. note 4: transit in accordance with arrow. (refer to the following for the transition of normal mode.) power control
49 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure 1.13.6 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control reg- ister 0 (address 0006 16 ), system clock control register 1 (address 0007 16 ), port p9 direction register (ad- dress 03f3 16 ) , si/o3 control register (address 0362 16 ) and si/o4 control register (address 0366 16 ) can only be changed when the respective bit in the protect register is set to 1. therefore, important outputs can be allocated to port p9. if, after 1 (write-enabled) has been written to the port p9 direction register and si/oi control register (i=3,4) write-enable bit (bit 2 at address 000a 16 ), a value is written to any address, the bit automatically reverts to 0 (write-inhibited). however, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000a 16 ) and processor mode register 0 and 1 write-enable bit (bit 1 at 000a 16 ) do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0. protect register symbol address when reset prcr 000a 16 xxxxx000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write-inhibited 1 : write-enabled prc1 prc0 prc2 enables writing to processor mode registers 0 and 1 (addresses 0004 16 and 0005 16 ) function 0 : write-inhibited 1 : write-enabled enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) enables writing to port p9 direction register (address 03f3 16 ) (note 1 ) 0 : write-inhibited 1 : write-enabled w r nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. note 1: writing a value to an address after ??is written to this bit returns the bit to ??. other bits do not automatically return to ??and they must therefore be reset by the program. a aa a aa a aa figure 1.13.6. protect register protection
50 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt ? maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure 1.14.1. classification of interrupts interrupt ? ? ? ? ? ? ? ? ? software hardware ? ? ? ? ? special peripheral i/o (note) ? ? ? ? ? undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? ? ? ? ? ? reset _______ nmi ________ dbc watchdog timer single step address matched note: peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system. overview of interrupt type of interrupts figure 1.14.1 lists the types of interrupts.
51 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. ? undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. ? overflow interrupt an overflow interrupt occurs when executing the into instruction with the overflow flag (o flag) set to 1. the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub ? brk interrupt a brk interrupt occurs when executing the brk instruction. ? int interrupt an int interrupt occurs when assiging one of software interrupt numbers 0 through 63 and executing the int instruction. software interrupt numbers 0 through 31 are assigned to peripheral i/o interrupts, so executing the int instruction allows executing the same interrupt routine that a peripheral i/o interrupt does. the stack pointer (sp) used for the int interrupt is dependent on which software interrupt number is involved. so far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (u flag) when it accepts an interrupt request. if change the u flag to 0 and select the interrupt stack pointer (isp), and then execute an interrupt sequence. when returning from the interrupt routine, the u flag is returned to the state it was before the acceptance of interrupt re- quest. so far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
52 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are non-maskable interrupts. ? reset ____________ reset occurs if an l is input to the reset pin. _______ ? nmi interrupt _______ _______ an nmi interrupt occurs if an l is input to the nmi pin. ________ ? dbc interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. ? watchdog timer interrupt generated by the watchdog timer. ? single-step interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. with the debug flag (d flag) set to 1, a single-step interrupt occurs after one instruction is executed. ? address match interrupt an address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1. if an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. for address match interrupt, see 2.11 address match interrupt. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. the interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the int instruction uses. peripheral i/o interrupts are maskable interrupts. ? bus collision detection interrupt this is an interrupt that the serial i/o bus collision detection generates. ? dma0 interrupt, dma1 interrupt these are interrupts that dma generates. ? key-input interrupt ___ a key-input interrupt occurs if an l is input to the ki pin. ? a-d conversion interrupt this is an interrupt that the a-d converter generates. ? uart0, uart1, uart2/nack, si/o3 and si/o4 transmission interrupt these are interrupts that the serial i/o transmission generates. ? uart0, uart1, uart2/ack, si/o3 and si/o4 reception interrupt these are interrupts that the serial i/o reception generates. ? timer a0 interrupt through timer a4 interrupt these are interrupts that timer a generates ? timer b0 interrupt through timer b5 interrupt these are interrupts that timer b generates. ________ ________ ? int0 interrupt through int5 interrupt ______ ______ an int interrupt occurs if either a rising edge or a falling edge or a both edge is input to the int pin. note 1: _______ _______ in m30623 (80-pin package), can not use int 3 to int 5 as the interrupt factors, because _______ _______ p1 5 /d 13 /int 3 to p1 7 /d 15 /int 5 have no corresponding external pin.
53 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt interrupt source vector table addresses remarks address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction overflow fffe0 16 to fffe3 16 interrupt on into instruction brk instruction fffe4 16 to fffe7 16 if the vector contains ff 16 , program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 there is an address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use watchdog timer ffff0 16 to ffff3 16 ________ dbc (note) ffff4 16 to ffff7 16 do not use nmi ffff8 16 to ffffb 16 _______ external interrupt by input to nmi pin reset ffffc 16 to fffff 16 note: interrupts used for debugging purposes only. figure 1.14.2. format for specifying interrupt vector addresses aaaaaaaaa aaaaaaaaa mid address aaaaaaaaa aaaaaaaaa low address aaaaaaaaa aaaaaaaaa 0 0 0 0 high address aaaaaaaaa aaaaaaaaa 0 0 0 0 0 0 0 0 vector address + 0 vector address + 1 vector address + 2 vector address + 3 lsb msb interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure 1.14.2 shows the format for specifying the address. two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. ? fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 1.14.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. table 1.14.1. interrupts assigned to the fixed vector tables and addresses of vector tables
54 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt table 1.14.2. interrupts assigned to the variable vector tables and addresses of vector tables software interrupt number interrupt source vector table address address (l) to address (h) remarks cannot be masked i flag +0 to +3 (note 1) brk instruction software interrupt number 0 +44 to +47 (note 1) software interrupt number 11 +48 to +51 (note 1) software interrupt number 12 +52 to +55 (note 1) software interrupt number 13 +56 to +59 (note 1) software interrupt number 14 +68 to +71 (note 1) software interrupt number 17 +72 to +75 (note 1) software interrupt number 18 +76 to +79 (note 1) software interrupt number 19 +80 to +83 (note 1) software interrupt number 20 +84 to +87 (note 1) software interrupt number 21 +88 to +91 (note 1) software interrupt number 22 +92 to +95 (note 1) software interrupt number 23 +96 to +99 (note 1) software interrupt number 24 +100 to +103 (note 1) software interrupt number 2 5 +104 to +107 (note 1) software interrupt number 26 +108 to +111 (note 1) software interrupt number 27 +112 to +115 (note 1) software interrupt number 28 +116 to +119 (note 1) software interrupt number 29 +120 to +123 (note 1) software interrupt number 30 +124 to +127 (note 1) software interrupt number 31 +128 to +131 (note 1) software interrupt number 32 +252 to +255 (note 1) software interrupt number 63 to note 1: address relative to address in interrupt table register (intb). note 2: it is selected by interrupt request cause bit (bit 6, 7 in address 035f16 ). note 3: when iic mode is selected, nack and ack interrupts are selected. note 4: in m30623 (80-pin package), can not use int3 to int5 as the interrupt factor, because p1 5 /d 13 /int 3 to p1 7 /d 15 /int 5 have no corresponding external pin. cannot be masked i flag +40 to +43 (note 1) software interrupt number 10 +60 to +63 (note 1) software interrupt number 15 +64 to +67 (note 1) software interrupt number 16 +20 to +23 (note 1) software interrupt number 5 +24 to +27 (note 1) software interrupt number 6 +28 to +31 (note 1) software interrupt number 7 +32 to +35 (note 1) software interrupt number 8 +16 to +19 (note 1) int3 software interrupt number 4 +36 to +39 (note 1) si/o3/int4 software interrupt number 9 si/o4/int5 timer b3 timer b4 timer b5 (note 2, note 4) (note 2, note 4) to dma0 dma1 key input interrupt a-d uart0 transmit uart0 receive uart1 transmit uart1 receive timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 int0 int1 int2 software interrupt bus collision detection uart2 transmit/nack (note 3) uart2 receive/ack (note 3) (note 4) ? variable vector tables the addresses in the variable vector table can be modified, according to the users settings. indicate the first address using the interrupt table register (intb). the 256-byte area subsequent to the ad- dress the intb indicates becomes the area for the variable vector tables. one vector table comprises four bytes. set the first address of the interrupt routine in each vector table. table 1.14.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables.
55 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt interrupt control descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. what is described here does not apply to non-maskable interrupts. enable or disable a maskable interrupt using the interrupt enable flag (i flag), interrupt priority level selec- tion bit, or processor interrupt priority level (ipl). whether an interrupt request is present or absent is indicated by the interrupt request bit. the interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. also, the interrupt enable flag (i flag) and the ipl are located in the flag register (flg). figure 1.14.3 shows the memory map of the interrupt control registers.
56 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt figure 1.14.3. interrupt control registers symbol address when reset intiic (i=3) 0044 16 xx00x000 2 siic/intjic (i=4, 3) 0048 16 , 0049 16 xx00x000 2 (j=4, 5) intiic (i=0 to 2) 005d 16 to 005f 16 xx00x000 2 bit name functio n bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a aa ilvl0 ir pol nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge 1 : selects rising edge always set to 0 ilvl1 ilvl2 note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: in m30623(80-pin package), can not use int3 to int5 interrupts. always set int3ic to ??00??. each of int4ic and int5ic is shared with s3ic and s4ic, but in case of not using as s3ic and s4ic, always set to ??00??. note 3: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. (note 1) interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa aa aa a a bit name functio n bit symbol w r symbol address when reset tbiic(i=3 to 5) 0045 16 to 0047 16 xxxxx000 2 bcnic 004a 16 xxxxx000 2 dmiic(i=0, 1) 004b 16 , 004c 16 xxxxx000 2 kupic 004d 16 xxxxx000 2 adic 004e 16 xxxxx000 2 sitic(i=0 to 2) 0051 16 , 0053 16 , 004f 16 xxxxx000 2 siric(i=0 to 2) 0052 16 , 0054 16 , 0050 16 xxxxx000 2 taiic(i=0 to 4) 0055 16 to 0059 16 xxxxx000 2 tbiic(i=0 to 2) 005a 16 to 005c 16 xxxxx000 2 ilvl0 i r interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. (note 1) note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
57 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt interrupt enable flag (i flag) the interrupt enable flag (i flag) controls the enabling and disabling of maskable interrupts. setting this flag to 1 enables all maskable interrupts; setting it to 0 disables all maskable interrupts. this flag is set to 0 after reset. interrupt request bit the interrupt request bit is set to "1" by hardware when an interrupt is requested. after the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. the interrupt request bit can also be set to "0" by software. (do not set this bit to "1"). table 1.14.4. interrupt levels enabled according to the contents of the ipl table 1.14.3. settings of interrupt priority levels interrupt priority level select bit interrupt priority level priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high b2 b1 b0 enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 2 ipl 1 ipl 0 ipl interrupt priority level select bit and processor interrupt priority level (ipl) set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. when an interrupt request occurs, the interrupt priority level is compared with the ipl. the interrupt is enabled only when the priority level of the interrupt is higher than the ipl. therefore, setting the interrupt priority level to 0 disables the interrupt. table 1.14.3 shows the settings of interrupt priority levels and table 1.14.4 shows the interrupt levels enabled, according to the consist of the ipl. the following are conditions under which an interrupt is accepted: interrupt enable flag (i flag) = 1 interrupt request bit = 1 interrupt priority level > ipl the interrupt enable flag (i flag), the interrupt request bit, the interrupt priority select bit, and the ipl are independent, and they are not affected by one another.
58 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions (four when using the hold function) or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. rewrite the interrupt control register to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset
59 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading ad- dress 00000 16 . (2) saves the content of the flag register (flg) as it was immediately before the start of interrupt sequence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) to 0 (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed) (4) saves the content of the temporary register (note) within the cpu in the stack area. (5) saves the content of the program counter (pc) in the stack area. (6) sets the interrupt priority level of the accepted instruction in the ipl. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 1.14.4 shows the interrupt response time. instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated figure 1.14.4. interrupt response time
60 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt variation of ipl when interrupt request is accepted if an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. if an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in table 1.14.6 is set in the ipl. stack pointer (sp) value interrupt vector address 16-bit bus, without wait 8-bit bus, without wait even even odd (note 2) odd (note 2) even odd even odd 18 cycles (note 1) 19 cycles (note 1) 19 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) table 1.14.5. time required for executing the interrupt sequence indeterminate 123456789 1011 12 13 14 15 16 17 18 the indeterminate segment is dependent on the queue buffer. if the queue buffer is ready to take an instruction, a read cycle occurs. indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 indeterminate sp-2 sp-4 vec vec+2 pc bclk address bus data bus w r time (a) is dependent on the instruction under execution. thirty cycles is the maximum required for the divx instruction (without wait). time (b) is as shown in table 1.14.5. ________ note 1: add 2 cycles in the case of a dbc interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. note 2: locate an interrupt vector address in an even address, if possible. figure 1.14.5. time required for executing the interrupt sequence table 1.14.6. relationship between interrupts without interrupt priority levels and ipl interrupt sources without priority levels value set in the ipl _______ watchdog timer, nmi 7 reset 0 other not changed
61 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt saving registers in the interrupt sequence, only the contents of the flag register (flg) and that of the program counter (pc) are saved in the stack area. first, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the flg register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. figure 1.14.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. save other necessary registers at the beginning of the interrupt routine using software. using the pushm instruction alone can save all the registers except the stack pointer (sp). address content of previous stack stack area [sp] stack pointer value before interrupt occurs m m ?1 m ?2 m ?3 m ?4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m ?1 m ?2 m ?3 m ?4 address flag register (flg l ) content of previous stack stack area flag register (flg h ) program counter (pc h ) [sp] new stack pointer value content of previous stack m + 1 msb lsb program counter (pc l ) program counter (pc m ) figure 1.14.6. state of stack before and after acceptance of interrupt request
62 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt figure 1.14.7. operation of saving registers (2) stack pointer (sp) contains odd number [sp] (odd) [sp] ?1 (even) [sp] ?2(odd) [sp] ?3 (even) [sp] ?4(odd) [sp] ?5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) stack pointer (sp) contains even number [sp] (even) [sp] ?1(odd) [sp] ?2 (even) [sp] ?3(odd) [sp] ?4 (even) [sp] ?5 (odd) note: [sp] denotes the initial value of the stack pointer (sp) when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) saved simultaneously, all 8 bits flag register (flg h ) program counter (pc h ) flag register (flg h ) program counter (pc h ) the operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. if the content of the stack pointer (note) is even, the content of the flag register (flg) and the content of the program counter (pc) are saved, 16 bits at a time. if odd, their contents are saved in two steps, 8 bits at a time. figure 1.14.7 shows the operation of the saving registers. note: stack pointer indicated by u flag.
63 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt interrupt priority if there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. assign an arbitrary priority to maskable interrupts (peripheral i/o interrupts) using the interrupt priority level select bit. if the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. priorities of the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. figure 1.14.8 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. returning from an interrupt routine executing the reit instruction at the end of an interrupt routine returns the contents of the flag register (flg) as it was immediately before the start of interrupt sequence and the contents of the program counter (pc), both of which have been saved in the stack area. then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. return the other registers saved by software within the interrupt routine using the popm or similar instruc- tion before executing the reit instruction. interrupt resolution circuit when two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. figure 1.14.9 shows the circuit that judges the interrupt priority level. figure 1.14.8. hardware interrupts priorities _______ ________ reset > nmi > dbc > watchdog timer > peripheral i/o > single step > address match
64 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt figure 1.14.9. maskable interrupts priorities (peripheral i/o interrupts) timer b2 timer b0 timer a3 timer a1 timer b1 timer a4 timer a2 uart1 reception uart0 reception uart2 reception/ack a-d conversion dma1 bus collision detection timer a0 uart1 transmission uart0 transmission uart2 transmission/nack key input interrupt dma0 processor interrupt priority level (ipl) interrupt enable flag (i flag) int1 int2 int0 watchdog timer reset dbc nmi interrupt request accepted level 0 (initial value) priority level of each interrupt high low priority of peripheral i/o interrupts (if priority levels are same) timer b4 int3 timer b3 timer b5 serial i/o4/int5 serial i/o3/int4 address match note 1: in m30623 (80-pin package), can not use int3 to int5 as the interrupt factors, because p1 5 /d 13 /int3 to p1 7 /d 15 /int5 have no corresponding external pin.
65 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development ______ int interrupt ________ ________ int0 to int5 are triggered by the edges of external inputs. the edge polarity is selected using the polarity select bit. ________ of interrupt control registers, 0048 16 is used both as serial i/o4 and external interrupt int5 input control ________ register, and 0049 16 is used both as serial i/o3 and as external interrupt int4 input control register. use the interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register (035f 16 ) - to specify which interrupt request cause to select. after having set an interrupt request cause, be sure to clear the corresponding interrupt request bit before enabling an interrupt. either of the interrupt control registers - 0048 16 , 0049 16 - has the polarity-switching bit. be sure to set this bit to 0 to select an serial i/o as the interrupt request cause. as for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting 1 in the inti interrupt polarity switching bit of the interrupt request cause select register (035f 16 ). to select both edges, set the polarity switching bit of the corresponding interrupt control register to falling edge (0). figure 1.14.10 shows the interrupt request cause select register. note 1: _______ _______ in m30623(80-pin package), can not use int3 to int5 as the interrupt factor, because _______ _______ p1 5 /d 13 /int 3 to p1 7 /d 15 /int 5 have no corresponding external pin. figure 1.14.10. interrupt request cause select register interrupt request cause select register bit name fumction bit symbol w r symbol address when reset ifsr 035f 16 00 16 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a aa aa a a int0 interrupt polarity swiching bit 0 : sio3 1 : int4 0 : sio4 1 : int5 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges int1 interrupt polarity swiching bit int2 interrupt polarity swiching bit int3 interrupt polarity swiching bit int4 interrupt polarity swiching bit int5 interrupt polarity swiching bit 0 : one edge 1 : two edges interrupt request cause select bit interrupt request cause select bit ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 ifsr6 ifsr7 a a a a a a a a a a a a a a a a a a a a a a note 1: in m30623(80-pin package), can not use int3 to int5 interrupts, so setting data of these bits are invalid. note 2: in m30623(80-pin package), can not use int3 to int5 interrupts. ______ int interrupt
66 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development interrupt control circuit key input interrupt control register (address 004d 16 ) key input interrupt request p10 7 /ki 3 p10 6 /ki 2 p10 5 /ki 1 p10 4 /ki 0 port p10 4 -p10 7 pull-up select bit port p10 7 direction register pull-up transistor port p10 7 direction register port p10 6 direction register port p10 5 direction register port p10 4 direction register pull-up transistor pull-up transistor pull-up transistor figure 1.14.11. block diagram of key input interrupt ______ nmi interrupt ______ ______ ______ an nmi interrupt is generated when the input to the p8 5 /nmi pin changes from h to l. the nmi interrupt is a non-maskable external interrupt. the pin level can be checked in the port p8 5 register (bit 5 at address 03f0 16 ). this pin cannot be used as a normal port input. key input interrupt if the direction register of any of p10 4 to p10 7 is set for input and a falling edge is input to that port, a key input interrupt is generated. a key input interrupt can also be used as a key-on wakeup function for cancel- ling the wait mode or stop mode. however, if you intend to use the key input interrupt, do not use p10 4 to p10 7 as a-d input ports. figure 1.14.11 shows the block diagram of the key input interrupt. note that if an l level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. _______ nmi interrupt
67 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the inter- rupt enable flag (i flag) and processor interrupt priority level (ipl). the value of the program counter (pc) for an address match interrupt varies depending on the instruction being executed. figure 1.14.12 shows the address match interrupt-related registers. bit name bit symbol symbol address when reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function w r aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 aaaaaaaaaaaaaa aaaaaaaaaaaaaa symbol address when reset rmad0 0012 16 to 0010 16 x00000 16 rmad1 0016 16 to 0014 16 x00000 16 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminated. b7 b6 b5 b4 b3 b2 b1 b0 w r address setting register for address match interrupt function values that can be set address match interrupt register i (i = 0, 1) 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminated. 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 b3 (b19) (b16) b7 b0 (b15) (b8) b7 (b23) aa a aa a aa aa a a figure 1.14.12. address match interrupt-related registers address match interrupt
68 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development precautions for interrupts (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in _______ the stack pointer before accepting an interrupt. when using the nmi interrupt, initialize the stack point at the beginning of a program. concerning the first instruction immediately after reset, generating any _______ interrupts including the nmi interrupt is prohibited. _______ (3) the nmi interrupt _______ ? as for the nmi interrupt pin, an interrupt cannot be disabled. connect it to the vcc pin via a resistor (pull-up) if unused. be sure to work on it. _______ ? the nmi pin also serves as p8 5 , which is exclusively input. reading the contents of the p8 register allows reading the pin value. use the reading of this pin only for establishing the pin level at the time _______ when the nmi interrupt is input. _______ ? do not reset the cpu with the input to the nmi pin being in the l state. _______ ? do not attempt to go into stop mode with the input to the nmi pin being in the l state. with the input to _______ the nmi being in the l state, the cm10 is fixed to 0, so attempting to go into stop mode is turned down. _______ ? do not attempt to go into wait mode with the input to the nmi pin being in the l state. with the input to _______ the nmi pin being in the l state, the cpu stops but the oscillation does not stop, so no power is saved. in this instance, the cpu is returned to the normal state by a later interrupt. _______ ? signals input to the nmi pin require an "l" level of 1 clock or more, from the operation clock of the cpu. (4) external interrupt ________ ? either an l level or an h level of at least 250 ns width is necessary for the signal input to pins int 0 ________ through int 5 regardless of the cpu operation clock. ________ ________ ? when the polarity of the int 0 to int 5 pins is changed, the interrupt request bit is sometimes set to "1". after changing the polarity, set the interrupt request bit to "0". figure 1.14.13 shows the procedure for ______ changing the int interrupt generate factor. note 1: _______ _______ in m30623(80-pin package), can not use int3 to int5 as the interrupt factor,because _______ _______ p1 5 /d 13 /int 3 to p1 7 /d 15 /int 5 have no corresponding external pin. precautions for interrupts
69 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development ______ figure 1.14.13. switching condition of int interrupt request set the polarity select bit clear the interrupt request bit to ? set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) clear the interrupt enable flag to ? (disable interrupt) set the interrupt enable flag to ? (enable interrupt) precautions for interrupts example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions (four when using the hold function) or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) rewrite the interrupt control register ? to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: ? when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset
70 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development watchdog timer watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the bclk using the prescaler. a watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. when x in is selected for the bclk , bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). when x cin is selected as the bclk, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000f 16 ). thus the watchdog timer's period can be calcu- lated as given below. the watchdog timer's period is, however, subject to an error due to the pre-scaler. bclk write to the watchdog timer start register (address 000e 16 ) reset watchdog timer interrupt request watchdog timer set to ?fff 16 1/128 1/16 ?m07 = 0 ?dc7 = 1 ?m07 = 0 ?dc7 = 0 ?m07 = 1 hold 1/2 prescaler for example, suppose that bclk runs at 10 mhz and that 16 has been chosen for the dividing ratio of the pre-scaler, then the watchdog timer's period becomes approximately 52.4 ms. the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the microcomputer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). figure 1.15.1 shows the block diagram of the watchdog timer. figure 1.15.2 shows the watchdog timer- related registers. with x in chosen for bclk watchdog timer period = pre-scaler dividing ratio (16 or 128) x watchdog timer count (32768) bclk figure 1.15.1. block diagram of watchdog timer with x cin chosen for bclk watchdog timer period = pre-scaler dividing ratio (2) x watchdog timer count (32768) bclk
71 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development watchdog timer watchdog timer control register symbol address when reset wdc 000f 16 00 ] xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to ?fff 16 regardless of whatever value is written. reserved bit must always be set to ? 0 0 a a a a a a a aa wdv5 0 : cold start 1 : warm start note 1: when this flag is written ??0?? or ??1??, it is set ??1?? automatically . ] : this bit is not under the influence of a reset. cold start / warm start discrimination flag (note 1) figure 1.15.2. watchdog timer control and start registers cold start / warm start the cold start/warm start discrimination flag(bit 5 at 000f 16 ) indicates the last reset by power on(cold start) or by reset signal(warm start). the cold start/warm start discrimination flag is set 0 at power on, and is set 1 at writing any data to the watchdog timer control register(address is 000f 16 ). the flag is not set to 0 by the software reset and the input of reset signal. figure 1.15.3. cold sgtart / warm start vcc 5v 0v 0v 5v 1 0 cold start / warm start discrimination flag (wdc5) reset 0.2vcc set to 1 by software
72 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer dmac dmac this microcomputer has two dmac (direct memory access controller) channels that allow data to be sent to memory without using the cpu. dmac shares the same data bus with the cpu. the dmac is given a higher right of using the bus than the cpu, which leads to working the cycle stealing method. on this account, the operation from the occurrence of dma transfer request signal to the completion of 1-word (16- bit) or 1-byte (8-bit) data transfer can be performed at high speed. figure 1.16.1 shows the block diagram of the dmac. table 1.16.1 shows the dmac specifications. figures 1.16.2 to 1.16.4 show the registers used by the dmac. figure 1.16.1. block diagram of dmac a a a a a a aa aa aa aa a a a aa aa aa aa aa a a a a a a data bus low-order bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) data bus high-order bits aa aa aa aa a a aa aa aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaa aaaaaaa address bus a a a a a a a a dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) aa aa aa dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) a a (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: pointer is incremented by a dma request. aa aa aa aa aa aa a a a a a a a a aa aa aa aa a a a a a a a either a write signal to the software dma request bit or an interrupt request signal is used as a dma transfer request signal. but the dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. the dma transfer doesn't affect any interrupts either. if the dmac is active (the dma enable bit is set to 1), data transfer starts every time a dma transfer request signal occurs. if the cycle of the occurrences of dma transfer request signals is higher than the dma transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. for details, see the description of the dma request bit.
73 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer dmac item specification no. of channels 2 (cycle steal method) transfer memory space ? from any address in the 1m bytes space to a fixed address ? from a fixed address to any address in the 1m bytes space ? from a fixed address to a fixed address (note that dma-related registers [0020 16 to 003f 16 ] cannot be accessed) maximum no. of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors (note) ________ ________ ________ ________ falling edge of int0 or int1 (int0 can be selected by dma0, int1 by dma1) or both edge timer a0 to timer a4 interrupt requests timer b0 to timer b5 interrupt requests uart0 transfer and reception interrupt requests uart1 transfer and reception interrupt requests uart2 transfer and reception interrupt requests serial i/o3, 4 interrpt requests a-d conversion interrupt requests software triggers channel priority dma0 takes precedence if dma0 and dma1 requests are generated simultaneously transfer unit 8 bits or 16 bits transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) transfer mode ? single transfer mode after the transfer counter underflows, the dma enable bit turns to 0, and the dmac turns inactive ? repeat transfer mode after the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. the dmac remains active unless a 0 is written to the dma enable bit. dma interrupt request generation timing when an underflow occurs in the transfer counter active when the dma enable bit is set to 1, the dmac is active. when the dmac is active, data transfer starts every time a dma transfer request signal occurs. inactive ? when the dma enable bit is set to 0, the dmac is inactive. ? after the transfer counter underflows in single transfer mode at the time of starting data transfer immediately after turning the dmac active, the value of one of source pointer and destination pointer - the one specified for the forward direction - is reloaded to the forward direction address pointer,and the value of the transfer counter reload register is reloaded to the transfer counter. writing to register registers specified for forward direction transfer are always write enabled. registers specified for fixed address transfer are write-enabled when the dma enable bit is 0. reading the register can be read at any time. however, when the dma enable bit is 1, reading the register set up as the forward register is the same as reading the value of the forward address pointer. table 1.16.1. dmac specifications note: dma transfer is not effective to any interrupt. dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. forward address pointer and reload timing for transfer counter
74 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer dmac dma0 request cause select register symbol address when reset dm0sl 03b8 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? software dma request bit if software trigger is selected, a dma request is generated by setting this bit to ?? (when read, the value of this bit is always ?? dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int0 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3 0 1 1 0 : timer a4 (dms=0) /two edges of int0 pin (dms=1) 0 1 1 1 : timer b0 (dms=0) timer b3 (dms=1) 1 0 0 0 : timer b1 (dms=0) timer b4 (dms=1) 1 0 0 1 : timer b2 (dms=0) timer b5 (dms=1) 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : uart1 transmit a a a a a a a a a a a a bit name dma request cause expansion bit dms 0 : normal 1 : expanded cause a a figure 1.16.2. dmac register (1)
75 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer dmac dmai control register symbol address when reset dmicon(i=0,1) 002c 16 , 003c 16 00000x00 2 bit name function bit symbol transfer unit bit select bit b7 b6 b5 b4 b3 b2 b1 b0 0 : 16 bits 1 : 8 bits dmbit rw dmasl dmas dmae repeat transfer mode select bit 0 : single transfer 1 : repeat transfer dma request bit (note 1) 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 0 : fixed 1 : forward dma enable bit source address direction select bit (note 3) destination address direction select bit (note 3) 0 : fixed 1 : forward dsd dad nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? note 1: dma request can be cleared by resetting the bit. note 2: this bit can only be set to ?? note 3: source address direction select bit and destination address direction select bit cannot be set to ??simultaneously. (note 2) a a a a a a a a a a a a a a dma1 request cause select register symbol address when reset dm1sl 03ba 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. software dma request bit if software trigger is selected, a dma request is generated by setting this bit to 1 (when read, the value of this bit is always 0) dsr b3 b2 b1 b0 0 0 0 0 : falling edge of int1 pin 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3(dms=0) /serial i/o3 (dms=1) 0 1 1 0 : timer a4 (dms=0) /serial i/o4 (dms=1) 0 1 1 1 : timer b0 (dms=0) /two edges of int1 (dms=1) 1 0 0 0 : timer b1 1 0 0 1 : timer b2 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart2 transmit 1 1 0 1 : uart2 receive 1 1 1 0 : a-d conversion 1 1 1 1 : uart1 receive a aa a a aa aa a aa a aa a aa bit name dma request cause expansion bit dms 0 : normal 1 : expanded cause a aa figure 1.16.3. dmac register (2)
76 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer dmac b7 b0 b7 b0 (b8) (b15) function rw ?transfer counter set a value one less than the transfer count symbol address when reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) transfer count specification 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw ?source pointer stores the source address symbol address when reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? symbol address when reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function rw ?destination pointer stores the destination address dmai destination pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 b7 (b23) nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? a a a a a a a aa figure 1.16.4. dmac register (3)
77 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer dmac (1) transfer cycle the transfer cycle consists of the bus cycle in which data is read from memory or from the sfr area (source read) and the bus cycle in which the data is written to memory or to the sfr area (destination write). the number of read and write bus cycles depends on the source and destination addresses. in memory expansion mode and microprocessor mode, the number of read and write bus cycles also de- pends on the level of the byte pin. also, the bus cycle itself is longer when software waits are inserted. (a) effect of source and destination addresses when 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) effect of byte pin level when transferring 16-bit data over an 8-bit data bus (byte pin = h) in memory expansion mode and microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. therefore, two bus cycles are required for reading the data and two are required for writing the data. also, in contrast to when the cpu accesses internal memory, when the dmac accesses internal memory (internal rom, internal ram, and sfr), these areas are accessed using the data size selected by the byte pin. (c) effect of software wait when the sfr area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. the length of the cycle is determined by bclk. figure 1.16.5 shows the example of the transfer cycles for a source read. for convenience, the destina- tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating the transfer cycle, remember to apply the respec- tive conditions to both the destination write cycle and the source read cycle. for example (2) in figure 1.16.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle. note 1: m30623(80-pin package), in case of access to the external bus area, can be used only when 8-bit bus mode.
78 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer dmac bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1) 8-bit transfers 16-bit transfers from even address and the source address is even. bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (3) one wait is inserted into the source read under the conditions in (1) bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) 16-bit transfers and the source address is odd transferring 16-bit data on an 8-bit data bus (in this case, there are also two destination write cycles). bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (4) one wait is inserted into the source read under the conditions in (2) (when 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles). note 1: the same timing changes occur with the respective conditions at the destination as at the source. note 2: m30623(80-pin package), in case of access to the external bus area, can be used only when 8-bit bus mode. figure 1.16.5. example of the transfer cycles for a source read
79 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer dmac single-chip mode memory expansion mode transfer unit bus width access address microprocessor mode no. of read no. of write no. of read no. of write cycles cycles cycles cycles 16-bit even 1 1 1 1 8-bit transfers (byte= l) odd 1 1 1 1 (dmbit= 1) 8-bit even 1 1 (byte = h) odd 1 1 16-bit even 1 1 1 1 16-bit transfers (byte = l) odd 2 2 2 2 (dmbit= 0) 8-bit even 2 2 (byte = h) odd 2 2 table 1.16.2. no. of dmac transfer cycles internal memory external memory internal rom/ram internal rom/ram sfr area separate bus separate bus multiplex no wait with wait no wait with wait bus 122123 coefficient j, k (2) dmac transfer cycles any combination of even or odd transfer read and write addresses is possible. table 1.16.2 shows the number of dmac transfer cycles. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k note 1: m30623(80-pin package), in case of access to the external bus area, can be used only when 8-bit bus mode.
80 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer dmac dma enable bit setting the dma enable bit to "1" makes the dmac active. the dmac carries out the following operations at the time data transfer starts immediately after dmac is turned active. (1) reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) reloads the value of the transfer counter reload register to the transfer counter. thus overwriting "1" to the dma enable bit with the dmac being active carries out the operations given above, so the dmac operates again from the initial state at the instant "1" is overwritten to the dma enable bit. dma request bit the dmac can generate a dma transfer request signal triggered by a factor chosen in advance out of dma request factors for each channel. dma request factors include the following. * factors effected by using the interrupt request signals from the built-in peripheral functions and software dma factors (internal factors) effected by a program. * external factors effected by utilizing the input from external interrupt signals. for the selection of dma request factors, see the descriptions of the dmai factor selection register. the dma request bit turns to "1" if the dma transfer request signal occurs regardless of the dmac's state (regardless of whether the dma enable bit is set "1" or to "0"). it turns to "0" immediately before data transfer starts. in addition, it can be set to "0" by use of a program, but cannot be set to "1". there can be instances in which a change in dma request factor selection bit causes the dma request bit to turn to "1". so be sure to set the dma request bit to "0" after the dma request factor selection bit is changed. the dma request bit turns to "1" if a dma transfer request signal occurs, and turns to "0" immediately before data transfer starts. if the dmac is active, data transfer starts immediately, so the value of the dma request bit, if read by use of a program, turns out to be "0" in most cases. to examine whether the dmac is active, read the dma enable bit. here follows the timing of changes in the dma request bit. (1) internal factors except the dma request factors triggered by software, the timing for the dma request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. turning the dma request bit to "1" due to an internal factor is timed to be effected immediately before the transfer starts. (2) external factors an external factor is a factor caused to occur by the leading edge of input from the inti pin (i depends on which dmac channel is used). selecting the inti pins as external factors using the dma request factor selection bit causes input from these pins to become the dma transfer request signals. the timing for the dma request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the dma request factor selection bit (synchronizes with the trailing edge of the input signal to each inti pin, for example). with an external factor selected, the dma request bit is timed to turn to "0" immediately before data transfer starts similarly to the state in which an internal factor is selected.
81 mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer dmac (3) the priorities of channels and dma transfer timing if a dma transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of bclk), the dma request bits of applicable channels concurrently turn to "1". if the channels are active at that moment, dma0 is given a high priority to start data transfer. when dma0 finishes data transfer, it gives the bus right to the cpu. when the cpu finishes single bus access, then dma1 starts data transfer and gives the bus right to the cpu. an example in which dma transfer is carried out in minimum cycles at the time when dma transfer request signals due to external factors concurrently occur. figure 1.16.6 an example of dma transfer effected by external factors. bclk aaaa aaaa dma0 aaaa dma1 dma0 request bit dma1 request bit aaa aaa aaaaa aaaaa a a aaaaaa aaaaaa aa aa cpu int0 int1 obtainm ent of the bus right an example in which dma transmission is carried out in minimum cycles at the time when dma transmission request signals due to external factors concurrently occur. figure 1.16.6. an example of dma transfer effected by external factors
82 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer timer there are eleven 16-bit timers. these timers can be classified by function into timers a (five) and timers b (six). all these timers function independently. figures 1.17.1 and 1.17.2 show the block diagram of timers. ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ta0 in ta1 in ta2 in ta3 in ta4 in timer a0 timer a1 timer a2 timer a3 timer a4 f 1 f 8 f 32 f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to ? reset clock prescaler timer b2 overflow note 1: in m30623(80-pin package), do not use ta1 in and ta2 in as the event input, because these are not connected to the external pin. and these pins have to do connection of unused pins (refer to page 170). note 2: the ta0 in pin (p7 1 ) is shared with rxd 2 and the tb5 in pin. figure 1.17.1. timer a block diagram
83 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer figure 1.17.2. timer b block diagram ? event counter mode ? event counter mode ? event counter mode ? timer mode ? pulse width measuring mode ? timer mode ? pulse width measuring mode ? timer mode ? pulse width measuring mode tb0 in tb1 in tb2 in timer b0 timer b1 timer b2 f 1 f 8 f 32 f c32 timer b0 interrupt noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to 1 reset clock prescaler timer a ? event counter mode ? event counter mode ? event counter mode ? timer mode ? pulse width measuring mode ? timer mode ? pulse width measuring mode ? timer mode ? pulse width measuring mode tb3 in tb4 in tb5 in timer b3 timer b4 timer b5 timer b3 interrupt noise filter noise filter noise filter timer b1 interrupt timer b2 interrupt timer b4 interrupt timer b5 interrupt note 1: in m30623(80-pin package), do not use tb1 in as the event input, because it is not connected to the external pin. and these pins have to do connection of unused pins (refer to page 170). note 2: the tb5 in pin ( p7 1 ) is shared with rxd 2 and the ta0 in pin.
84 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer a timer a figure 1.17.3 shows the block diagram of timer a. figures 1.17.4 to 1.17.6 show the timer a-related registers. except in event counter mode, timers a0 through a4 all have the same function. use the timer ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. but m30623(80-pin package), timer a1 and a2 have no i/o pin, so it operate as only internal timer. timer a has the four operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer over flow. ? one-shot timer mode: the timer stops counting when the count reaches 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses of a given width. figure 1.17.4. timer a-related registers (1) count start flag (address 0380 16 ) up count/down count tai addresses taj tak timer a0 0387 16 0386 16 timer a4 timer a1 timer a1 0389 16 0388 16 timer a0 timer a2 timer a2 038b 16 038a 16 timer a1 timer a3 timer a3 038d 16 038c 16 timer a2 timer a4 timer a4 038f 16 038e 16 timer a3 timer a0 always down count except in event counter mode reload register (16) counter (16) low-order 8 bits aaa aaa high-order 8 bits clock source selection timer (gate function) timer one shot pwm f 1 f 8 f 32 external trigger tai in (i = 0 to 4) tb2 overflow event counter f c32 clock selection taj overflow (j = i e 1. note, however, that j = 4 when i = 0) pulse output toggle flip-flop tai out (i = 0 to 4) data bus low-order bits data bus high-order bits aa aa up/down flag down count (address 0384 16 ) tak overflow (k = i + 1. note, however, that k = 0 when i = 4) polarity selection note 1: in m30623(80-pin package), do not select the function using ta1 in , ta1 out , or ta2 in , and ta2 out because these are not connected to the external pin. note 2: the ta0 in pin (p7 1 ) is shared with the tb5 in pin, rxd 2 , and scl pin. timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit a aa a aa a aa a aa a aa a aa a aa a a aa aa figure 1.17.3. block diagram of timer a
85 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer a figure 1.17.5. timer a-related registers (2) timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit symbol address when reset udf 0384 16 00 16 ta4p ta3p ta2p up/down flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud 0 : down count 1 : up count this specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled when not using the two-phase pulse signal processing function, set the select bit to 0 symbol address when reset tabsr 0380 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s symbol address when reset ta0 0387 16 ,0386 16 indeterminate ta1 0389 16 ,0388 16 indeterminate ta2 038b 16 ,038a 16 indeterminate ta3 038d 16 ,038c 16 indeterminate ta4 038f 16 ,038e 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer ai register (note) w r ? timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set ? event counter mode 0000 16 to ffff 16 counts pulses from an external source or timer overflow ? one-shot timer mode 0000 16 to ffff 16 counts a one shot width ? pulse width modulation mode (16-bit pwm) functions as a 16-bit pulse width modulator ? pulse width modulation mode (8-bit pwm) timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 00 16 to fe 16 (both high-order and low-order addresses) 0000 16 to fffe 16 note: read and write data in 16-bit units. note 1: m30623(80-pin package) does not have i/o pins for ta2, so set this bit to 0. (note 1)
86 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer a symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is 0) cpsr w r nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. ta1tgl symbol address when reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note 1, 2) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note 1, 2) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note 1) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note 1) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note 1: set the corresponding port direction register to 0. note 2: in m30623(80-pin package), do not select the function using ta1 in and ta2 in , because these are not connected to the external pin. ta1os ta2os ta0os one-shot start flag symbol address when reset onsf 0382 16 00x00000 2 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. ta0tgl ta0tgh 0 0 : input on ta0 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 note: set the corresponding port direction register to 0. w r 1 : timer start when read, the value is 0 a a aa aa a aa a aa a aa aa a aa a aa a aa a a aa aa a aa a a aa aa a a aa aa a aa a aa a aa a aa a aa a aa a a aa aa figure 1.17.6. timer a-related registers (3)
87 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer a item specification count source f 1 , f 8 , f 32 , f c32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when the timer underflows tai in pin function programmable i/o port or gate input tai out pin function programmable i/o port or pulse output read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? gate function counting can be started and stopped by the tai in pins input signal ? pulse output function each time the timer underflows, the tai out pins polarity is reversed (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.17.1.) figure 1.17.7 shows the timer ai mode register in timer mode. table 1.17.1. specifications of timer mode note 1: the settings of the corresponding port register and port direction register are invalid. note 2: the bit can be ??or ?? note 3: set the corresponding port direction register to ?? note 4: in timer a1 and a2 mode register of m30623(80-pin package), set these bits to ?? timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit (note 4) 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (ta iout pin is a pulse output pin) gate function select bit 0 x (note 2) : gate function not available (tai in pin is a normal port pin) 1 0 : timer counts only when ta iin pin is held ??(note 3) 1 1 : timer counts only when ta iin pin is held ??(note 3) b4 b3 mr2 mr1 mr3 0 (must always be fixed to ??in timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 00 0 a a a a a a a a a a a a a a a a a a a a (note 4) figure 1.17.7. timer ai mode register in timer mode note 1: m30623(80-pin package) does not have i/o pins(tai in ,tai out ) for timer a1 and a2.
88 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer a (2) event counter mode in this mode, the timer counts an external signal or an internal timers overflow. timers a0 and a1 can count a single-phase external signal. timers a2, a3, and a4 can count a single-phase and a two-phase external signal. table 1.17.2 lists timer specifications when counting a single-phase external signal. figure 1.17.8 shows the timer ai mode register in event counter mode. table 1.17.3 lists timer specifications when counting a two-phase external signal. figure 1.17.9 shows the timer ai mode register in event counter mode. figure 1.17.8. timer ai mode register in event counter mode timer ai mode register note 1: in event counter mode, the count source is selected by the event / trigger select bit (addresses 0382 16 and 0383 16 ). note 2: the settings of the corresponding port register and port direction register are invalid. note 3: valid only when counting an external signal. note 4: when an ??signal is input to the tai out pin, the downcount is activated. when ?? the upcount is activated. set the corresponding port direction register to ?? note 5: in timer a1 and a2 mode register of m30623(80-pin package), set these bits to ?? symbol address when reset taimr(i = 0, 1) 0396 16 , 0397 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 pulse output function select bit (note 5) 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 2) (ta iout pin is a pulse output pin) count polarity select bit (note 3,note 5) mr2 mr1 mr3 0 (must always be fixed to ??in event counter mode) tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit (note 5) 0 : up/down flag's content 1 : ta iout pin's input signal (note 4) 0 : reload type 1 : free-run type bit symbol bit name function rw tck1 invalid in event counter mode can be ??or ? tmod1 a a aa aa a aa a aa a aa aa a aa a aa a a aa aa a aa item specification count source ? external signals input to tai in pin (effective edge can be selected by software) ? tb2 overflow, taj overflow count operation ? up count or down count can be selected by external signal or software ? when the timer overflows or underflows, it reloads the reload register con tents before continuing counting (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer overflows or underflows tai in pin function programmable i/o port or count source input tai out pin function programmable i/o port, pulse output, or up/down count select input read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ? pulse output function each time the timer overflows or underflows, the tai out pins polarity is reversed note 1: this does not apply when the free-run function is selected. note 2: m30623(80-pin package) does not have i/o pins(tai in ,tai out ) for timer a1 and a2. table 1.17.2. timer specifications in event counter mode (when not processing two-phase pulse signal)
89 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer a item specification count source ? two-phase pulse signals input to tai in or tai out pin count operation ? up count or down count can be selected by two-phase pulse signal ? when the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing timer overflows or underflows tai in pin function two-phase pulse input tai out pin function two-phase pulse input read from timer count value can be read out by reading timer a2, a3, or a4 register write to timer ? when counting stopped when a value is written to timer a2, a3, or a4 register, it is written to both reload register and counter ? when counting in progress when a value is written to timer a2, a3, or a4 register, it is written to only reload register. (transferred to counter at next reload time.) select function ? normal processing operation the timer counts up rising edges or counts down falling edges on the tai in pin when input signal on the tai out pin is h ? multiply-by-4 processing operation if the phase relationship is such that the tai in pin goes h when the input signal on the tai out pin is h, the timer counts up rising and falling edges on the tai out and tai in pins. if the phase relationship is such that the tai in pin goes l when the input signal on the tai out pin is h, the timer counts down rising and falling edges on the tai out and tai in pins. note 1: this does not apply when the free-run function is selected. note 2: m30623(80-pin package) does not have i/o pins(tai in ,tai out ) for timer a1 and a2. table 1.17.3. timer specifications in event counter mode (when processing two-phase pulse signal with timers a2, a3, and a4) tai out up count up count up count down count down count down count tai in (i=2,3) tai out tai in (i=3,4) count up all edges count up all edges count down all edges count down all edges
90 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer a note 1: the settings of the corresponding port register and port direction register are invalid. note 2: this bit is valid when only counting an external signal. note 3: set the corresponding port direction register to ?? note 4: this bit is valid for the timer a3 mode register. for timer a2 and a4 mode registers, this bit can be ? ?r ?? note 5: set these bits to ?? in timer a2 mode register of m30623(80-pin package). timer ai mode register (when not using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit (note 5) 0 : pulse is not output (tai out pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) count polarity select bit (note 2,note 5) mr2 mr1 mr3 0 : (must always be ??in event counter mode) tck1 tck0 01 0 0 : counts external signal's falling edges 1 : counts external signal's rising edges up/down switching cause select bit (note 5) 0 : up/down flag's content 1 : ta iout pin's input signal (note 3) bit symbol bit name function w r count operation type select bit two-phase pulse signal processing operation select bit (note 4) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation note 1: this bit is valid for timer a3 mode register. for timer a2 and a4 mode registers, this bit can be ??or ?? note 2: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0384 16 ) is set to ?? also, always be sure to set the event/trigger select bit (addresses 0382 16 and 0383 16 ) to ?0? note 3: in m30623(80-pin package), do not use timer a2 for the two-phase pulse signal processing. timer ai mode register (when using two-phase pulse signal processing) symbol address when reset taimr(i = 2 to 4) 0398 16 to 039a 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 0 (must always be ??when using two-phase pulse signal processing) 0 (must always be ??when using two-phase pulse signal processing) mr2 mr1 mr3 0 (must always be ??when using two-phase pulse signal processing) tck1 tck0 01 0 1 (must always be ??when using two-phase pulse signal processing) bit symbol bit name function w r count operation type select bit two-phase pulse processing operation select bit (note 1)(note 2) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation 0 0 1 a aa a aa a a aa aa a aa a aa a aa a aa a aa a a aa aa a aa a aa a aa a aa a aa a aa a aa figure 1.17.9. timer ai mode register in event counter mode
91 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer a item specification count source f 1 , f 8 , f 32 , f c32 count operation ? the timer counts down ? when the count reaches 0000 16 , the timer stops counting after reloading a new count ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition ? an external trigger is input ? the timer overflows ? the one-shot start flag is set (= 1) count stop condition ? a new count is reloaded after the count has reached 0000 16 ? the count start flag is reset (= 0) interrupt request generation timing the count reaches 0000 16 tai in pin function programmable i/o port or trigger input tai out pin function programmable i/o port or pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) table1.17.4. timer specifications in one-shot timer mode figure 1.17.10. timer ai mode register in one-shot timer mode (3) one-shot timer mode in this mode, the timer operates only once. (see table 1.17.4.) when a trigger occurs, the timer starts up and continues operating for a given period. figure 1.17.10 shows the timer ai mode register in one-shot timer mode. bit name timer ai mode register symbol address when reset taimr(i = 0 to 4) 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit (note 4) 0 : pulse is not output (ta iout pin is a normal port pin) 1 : pulse is output (note 1) (tai out pin is a pulse output pin) mr2 mr1 mr3 0 (must always be ??in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 0 : one-shot start flag is valid 1 : selected by event/trigger select register trigger select bit external trigger select bit (note 2) (note 4) 0 : falling edge of tai in pin's input signal (note 3) 1 : rising edge of tai in pin's input signal (note 3) note 1: the settings of the corresponding port register and port direction register are invalid. note 2: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be ??or ?? note 3: set the corresponding port direction register to ?? note 4: set these bits to ?? in timer a1 and a2 mode register of m30623(80-pin package). w r aa a aa aa a a aa a aa a aa aa a a aa a aa a aa a note 1: m30623(80-pin package) does not have i/o pins(tai in ,tai out ) for timer a1 and a2.
92 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer a (4) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 1.17.5.) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure 1.17.11 shows the timer ai mode register in pulse width modulation mode. figure 1.17.12 shows the example of how a 16-bit pulse width modulator operates. figure 1.17.13 shows the example of how an 8- bit pulse width modulator operates. figure 1.17.11. timer ai mode register in pulse width modulation mode table 1.17.5. timer specifications in pulse width modulation mode bit name timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit w r 11 1 1 (must always be ??in pwm mode) (note 3) 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (note 1) (note 3) 0: falling edge of tai in pin's input signal (note 2) 1: rising edge of tai in pin's input signal (note 2) 0: count start flag is valid 1: selected by event/trigger select register note 1: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0382 16 and 0383 16 ). if timer overflow is selected, this bit can be ??or ?? note 2: set the corresponding port direction register to ?? note 3: set these bits to ?? in timer a1 and a2 mode register of m30623(80-pin package). a aa a a aa aa a aa a aa a aa a aa a aa a aa item specification count source f 1 , f 8 , f 32 , f c32 count operation ? t he timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new count at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs when counting 16-bit pwm ? high level width n / fi n : set value ? cycle time (2 16 -1) / fi fixed 8-bit pwm ? high level width n (m+1) / fi n : values set to timer ai registers high-order address ? cycle time (2 8 - 1) (m+1) / fi m : values set to timer ai registers low-order address count start condition ? external trigger is input ? the timer overflows ? the count start flag is set (= 1) count stop condition ? the count start flag is reset (= 0) interrupt request generation timing pwm pulse goes l tai in pin function programmable i/o port or trigger input tai out pin function pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) note 1: m30623(80-pin package) does not have i/o pins(tai in ,tai out ) for timer a1 and a2.
93 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer a 1 / f i x (2 ?1) 16 count source ta iin pin input signal pwm pulse output from ta iout pin condition : reload register = 0003 16 , when external trigger (rising edge of ta iin pin input signal) is selected trigger is not generated by this signal ? ? ? ? timer ai interrupt request bit ? ? cleared to ??when interrupt request is accepted, or cleared by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note 1: m30623(80-pin package) does not have i/o pins(taiin,taiout) for timer a1 and a2. note 2: n = 0000 16 to fffe 16 . 1 / f i x n count source (note1) ta iin pin input signal underflow signal of 8-bit prescaler (note2) pwm pulse output from ta iout pin(note 3) ? ? ? ? ? ? ? ? timer ai interrupt request bit cleared to ??when interrupt request is accepted, or cleaerd by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m30623(80-pin package) does not have no i/o pins(taiin,taiout) for timer a1 and a2. note 4: m = 00 16 to fe 16 ; n = 00 16 to fe 16 . aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa condition : reload register high-order 8 bits = 02 16 reload register low-order 8 bits = 02 16 external trigger (falling edge of ta iin pin input signal) is selected 1 / f i x (m + 1) x (2 e 1) 8 1 / f i x (m + 1) x n 1 / f i x (m + 1) (note 3) figure 1.17.12. example of how a 16-bit pulse width modulator operates figure 1.17.13. example of how an 8-bit pulse width modulator operates
94 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer b timer b figure 1.17.14 shows the block diagram of timer b. figures 1.17.15 and 1.17.16 show the timer b-related registers. use the timer bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. timer b has three operation modes listed as follows: figure 1.17.15. timer b-related registers (1) timer bi mode register symbol address when reset tbimr(i = 0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode (note 3) 1 1 : inhibited b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit (note 1) (note 2) note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. note 3: in the timer b1 mode register of m30623(80-pin package), do not use this mode, because timer b1 has no input pin. a a a a a a a a a a a a a a a a a a a clock source selection (address 0380 16 ) event counter timer pulse period/pulse width measurement reload register (16) low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 f 8 f 32 tbj overflow (j = i e 1. note, however, j = 2 when i = 0, j = 5 when i = 3) can be selected in only event counter mode count start flag f c32 polarity switching and edge pulse tbi in (i = 0 to 5) counter reset circuit counter (16) tbi address tbj timer b0 0391 16 0390 16 timer b2 timer b1 0393 16 0392 16 timer b0 timer b2 0395 16 0394 16 timer b1 timer b3 0351 16 0350 16 timer b5 timer b4 0353 16 0352 16 timer b3 timer b5 0355 16 0354 16 timer b4 note 1: in m30623(80-pin package), do not select the function using tb1 in , because it is not connected to the external pin. note 2: the tb5 in pin is shared with the ta0 in pin, rxd 2 , and scl pin. ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer overflow. ? pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. figure 1.17.14. block diagram of timer b but, m30623(80-pin package), timer b1 has no input pin, so funcs as the internal timer.
95 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer b note 1: read and write data in 16-bit units. note 2: in the timer b1 of m30623(80-pin package), do not select the external pulses input as count source, because timer b1 has no input pin. note 3: in the timer b1 of m30623(80-pin package), this mode does not function, because timer b1 has no input pin. symbol address when reset tabsr 0380 16 00 16 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function a aa a a aa aa a aa a aa a a aa aa a aa a aa a a aa aa symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa a aaaaaaaaaaaaa a aaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is ?? cpsr a aa symbol address when reset tb0 0391 16 , 0390 16 indeterminate tb1 0393 16 , 0392 16 indeterminate tb2 0395 16 , 0394 16 indeterminate tb3 0351 16 , 0350 16 indeterminate tb4 0353 16 , 0352 16 indeterminate tb5 0355 16 , 0354 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (note) w r pulse period / pulse width measurement mode measures a pulse period or width timer mode 0000 16 to ffff 16 counts the timer's period function values that can be set event counter mode 0000 16 to ffff 16 counts external pulses input or a timer overflow a aa a aa a a symbol address when reset tbsr 0340 16 00 16 timer b3, 4, 5 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa timer b5 count start flag timer b4 count start flag timer b3 count start flag 0 : stops counting 1 : starts counting tb5s tb4s tb3s nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. function a aa a aa a a aa aa nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. (note 3) (note 2) figure 1.17.16. timer b-related registers (2)
96 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer b count source f 1 , f 8 , f 32 , f c32 count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function programmable i/o port read from timer count value is read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be 0 or 1 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 invalid in timer mode. in an attempt to write to this bit, write 0. the value, if read in timer mode, turns out to be indeterminate. 0 0 (fixed to 0 in timer mode ; i = 0, 3) nothing is assiigned (i = 1, 2, 4, 5). in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. (note 1) (note 2) b7 b6 a aa a aa a a aa aa a aa a aa a aa a aa a a note 1: m30623(80-pin package) does not have the input pin(tb1 in ) of timer b1. (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.17.6.) figure 1.17.17 shows the timer bi mode register in timer mode. figure 1.17.17. timer bi mode register in timer mode table 1.17.6. timer specifications in timer mode item specification
97 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer b item specification count source ? external signals input to tbi in pin ? effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function count source input read from timer count value can be read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) (2) event counter mode in this mode, the timer counts an external signal or an internal timer's overflow. (see table 1.17.7.) figure 1.17.18 shows the timer bi mode register in event counter mode. table 1.17.7. timer specifications in event counter mode figure 1.17.18. timer bi mode register in event counter mode timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (note 1) mr2 mr1 mr3 invalid in event counter mode. in an attempt to write to this bit, write 0. the value, if read in event counter mode, turns out to be indeterminate. tck1 tck0 01 0 0 : counts external signal's falling edges 0 1 : counts external signal's rising edges 1 0 : counts external signal's falling and rising edges 1 1 : inhibited b3 b2 nothing is assigned (i = 1, 2, 4, 5). in an attempt to write to this bit, write 0. the value, if read, turns out to be indeterminate. note 1: valid only when input from the tbi in pin is selected as the event clock. if timer's overflow is selected, this bit can be 0 or 1. in timer b1 mode register of m30623(80-pin package), this bit is invalid. note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. note 4: set the corresponding port direction register to 0. in m30623(80-pin package), do not use the input from tb1 in pin as event clock, because there is no tb1 in pin. invalid in event counter mode. can be 0 or 1. event clock select 0 : input from tbi in pin (note 4) 1 : tbj overflow (j = i e 1; however, j = 2 when i = 0, j = 5 when i = 3) 0 (fixed to 0 in event counter mode; i = 0, 3) (note 2) (note 3) a a a a a a a a a a a a a a a a a note 1: m30623(80-pin package) does not have the input pin(tb1 in ) of timer b1.
98 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer b item specification count source f 1 , f 8 , f 32 , f c32 count operation ? up count ? counter value 0000 16 is transferred to reload register at measurement pulse's effective edge and the timer continues counting count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing ? when measurement pulse's effective edge is input (note 1) ? when an overflow occurs. (simultaneously, the timer bi overflow flag changes to 1. the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register.) tbi in pin function measurement pulse input read from timer when timer bi register is read, it indicates the reload registers content (measurement result) (note 2) write to timer cannot be written to table 1.17.8. timer specifications in pulse period/pulse width measurement mode figure 1.17.19. timer bi mode register in pulse period/pulse width measurement mode note 1: an interrupt request is not generated when the first effective edge is input after the timer has started counting. note 2: the value read out from the timer bi register is indeterminate until the second effective edge is input after the timer. timer bi mode register symbol address when reset tbimr(i=0 to 5) 039b 16 to 039d 16 00xx0000 2 035b 16 to 035d 16 00xx0000 2 bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr2 mr1 mr3 tck1 tck0 0 1 0 0 : pulse period measurement (interval between measurement pulse's falling edge to falling edge) 0 1 : pulse period measurement (interval between measurement pulse's rising edge to rising edge) 1 0 : pulse width measurement (interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : inhibited function b3 b2 nothing is assigned (i = 1, 2, 4, 5). in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate. count source select bit timer bi overflow flag ( note 1) 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note 1: the timer bi overflow flag changes to ??when the count start flag is ??and a value is written to the timer bi mode register. this flag cannot be set to ??by software. note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. 0 (fixed to ??in pulse period/pulse width measurement mode; i = 0, 3) (note 2) (note 3) aa a aa a aa a aa a aa a aa aa a a aa aa a a aa (3) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table 1.17.8.) m30623(80-pin package), timer b1 has no input pin, so can not use this function. figure 1.17.19 shows the timer bi mode register in pulse period/pulse width measurement mode. figure 1.17.20 shows the operation timing when measuring a pulse period. figure 1.17.21 shows the operation timing when measuring a pulse width
99 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timer b figure 1.17.21. operation timing when measuring a pulse width measurement pulse ? count source count start flag timer bi interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (measured value) transfer (measured value) ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) transfer (measured value) (note 1) cleared to ??when interrupt request is accepted, or cleared by software. (note 2) transfer (indeterminate value) reload register counter transfer timing figure 1.17.20. operation timing when measuring a pulse period count source measurement pulse count start flag timer bi interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (indeterminate value) ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) when measuring measurement pulse time interval from falling edge to falling edge (note 2) cleared to ??when interrupt request is accepted, or cleared by software. transfer (measured value) ? reload register counter transfer timing
100 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control three-phase pwm control register 0 symbol address when reset invc0 0348 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 effective interrupt output polarity select bit (note4) inv00 bit symbol bit name description rw inv01 effective interrupt output specification bit (note4) inv02 mode select bit (note 2) inv04 positive and negative phases concurrent l output disable function enable bit inv07 software trigger bit inv06 modulation mode select bit (note 3) inv05 positive and negative phases concurrent l output detect flag inv03 output control bit 0: a timer b2 interrupt occurs when the timer a1 reload control signal is ?? 1: a timer b2 interrupt occurs when the timer a1 reload control signal is ?? effective only in three-phase mode 1 0: not specified. 1: selected by the effective interrupt output polarity selection bit. effective only in three-phase mode 1 0: normal mode 1: three-phase pwm output mode 0: output disabled 1: output enabled 0: feature disabled 1: feature enabled 0: not detected yet 1: already detected 0: triangular wave modulation mode 1: sawtooth wave modulation mode 1: trigger generated the value, when read, is ?? (note 1) note 1: note 2: note 3: note 4: no value other than ??can be written. selecting three-phase pwm output mode causes p8 0 , p8 1 , and p7 2 through p7 5 to output u, u, v, v, w, and w, and works the timer for setting short circuit prevention time, the u, v, w phase output control circuits, and the circuit for setting timer b 2 interrupt frequency. in triangular wave modulation mode: the short circuit prevention timer starts in synchronization with the falling edge of timer ai output. the data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchroniz ation with the transfer trigger signal after writing to the three-phase output buffer register. in sawtooth wave modulation mode: the short circuit prevention timer starts in synchronization with the falling edge of timer a output and with the transfer trig ger signal. the data transfer from the three-phase output buffer register to the three-phase output shift register is made with respect to every transfer trigger. to write ??both to bit 0 (inv00) and bit 1 (inv01) of the three-phase pwm control register, set in advance the content of the timer b2 interrupt occurrences frequency set counter. t hree-phase pwm control register 1 symbol address when reset invc1 0349 16 00 16 bit name description bit symbol w r inv10 inv11 inv12 timer ai start trigger signal select bit timer a1-1, a2-1, a4-1 control bit short circuit timer count source select bit 0: timer b2 overflow signal 1: timer b2 overflow signal, signal for writing to timer b2 0: three-phase mode 0 1: three-phase mode 1 0 : not to be used 1 : f 1 /2 b7 b6 b5 b4 b3 b2 b1 b0 noting is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? noting is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be ?? reserved bit always set to ? 0 note 1: to use three-phase pwm output mode, write ??to inv12. figure1.18.1. registers related to timers for three-phase motor control timers?functions for three-phase motor control u se of more than one built-in timer a and timer b provides the means of outputting three-phase motor driving waveforms. __ ___ in m30623(80-pin package), the pins v, v, w, and w for three-phase motor control have no corresponding external pin. so, do not use this function. figures 1.18.1 to 1.18.3 show registers related to timers for three-phase motor control.
101 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control three-phase output buffer register 0 symbol address when reset idb0 034a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? du0 dub0 dv0 dw0 dvb0 dwb0 u phase output buffer 0 setting in u phase output buffer 0 v phase output buffer 0 w phase output buffer 0 u phase output buffer 0 v phase output buffer 0 w phase output buffer 0 setting in v phase output buffer 0 setting in w phase output buffer 0 setting in w phase output buffer 0 setting in v phase output buffer 0 setting in u phase output buffer 0 three-phase output buffer register 1 symbol address when reset idb1 034b 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? du1 dub1 dv1 dw1 dvb1 dwb1 u phase output buffer 1 setting in u phase output buffer 1 v phase output buffer 1 w phase output buffer 1 u phase output buffer 1 v phase output buffer 1 w phase output buffer 1 setting in v phase output buffer 1 setting in w phase output buffer 1 setting in w phase output buffer 1 setting in v phase output buffer 1 setting in u phase output buffer 1 dead time timer symbol address when reset dot 034c 16 indeterminate function values that can be set w r b7 b0 set dead time timer 1 to 255 timer b2 interrupt occurrences frequency set counter symbol address when reset ictb2 034d 16 indeterminate function values that can be set w r b3 b0 set occurrence frequency of timer b2 interrupt request 1 to 15 note: when executing read instruction of this register, the contents of three-phase shift register is read out. note: when executing read instruction of this register, the contents of three-phase shift register is read out. note1: in setting 1 to bit 1 (inv01) - the effective interrupt output specification bit - of three- phase pwm control register 0, do not change the b2 interrupt occurrences frequency set counter to deal with the timer function for three-phase motor control. note2: do not write at the timing of an overflow occurrence in timer b2. figure 1.18.2. registers related to timers for three-phase motor control
102 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control figure 1.18.3. registers related to timers for three-phase motor control symbol address when reset ta11 0343 16 ,0342 16 indeterminate ta21 0345 16 ,0344 16 indeterminate ta41 0347 16 ,0346 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r counts an internal count source 0000 16 to ffff 16 function values that can be set timer ai-1 register (note) note: read and write data in 16-bit units. a a symbol address when reset ta1 0389 16 ,0388 16 indeterminate ta2 038b 16 ,038a 16 indeterminate ta4 038f 16 ,038e 16 indeterminate tb2 0395 16 ,0394 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set one-shot timer mode 0000 16 to ffff 16 counts a one shot width note: read and write data in 16-bit units. timer ai register (note) a a a ta1tgl symbol address when reset trgsr 0383 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port direction register to 0. a aa a aa a aa a a aa aa a a aa aa a a aa aa a a aa aa a aa a aa b7 b6 b5 b4 b3 b2 b1 symbol address when reset tabsr 0380 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s a a a a a a a a a a a a a a a a a a a a a a
103 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control bit name timer ai mode register symbol address when reset ta1mr 0397 16 00 16 ta2mr 0398 16 00 16 ta3mr 039a 16 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 pulse output function select bit 0 (must always be ??in three-phase pwm output mode) mr2 mr1 mr3 0 (must always be ??in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 1 : selected by event/trigger select register trigger select bit external trigger select bit w r a a a a a a a a a a a a a a a a a a timer b2 mode register symbol address when reset tb2mr 039d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a aa operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be 0 or 1 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 invalid in timer mode. this bit can neither be set nor reset. when read in timer mode, its content is indeterminate. 0 0 (fixed to 0 in timer mode ; i = 0) b7 b6 a a a a a a a a a a a a a a a a a a a 1 0 invalid in three-phase pwm output mode can be 0 or 1 figure 1.18.4. timer mode registers in three-phase waveform mode three-phase motor driving waveform output mode (three-phase waveform mode) setting 1 in the mode select bit (bit 2 at 0348 16 ) shown in figure 1.18.1 - causes three-phase waveform mode that uses four timers a1, a2, a4, and b2 to be selected. as shown in figure 1.18.4, set timers a1, a2, and a4 in one-shot timer mode, set the trigger in timer b2, and set timer b2 in timer mode using the respective timer mode registers.
104 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control figure 1.18.5 shows the block diagram for three-phase waveform mode. in three-phase waveform mode, ___ ___ the positive-phase waveforms (u phase, v phase, and w phase) and negative waveforms (u phase, v ___ phase, and w phase), six waveforms in total, are output from p8 0 ,p8 1 , p7 2 , p7 3 , p7 4 , and p7 5 as active ___ on the l level. of the timers used in this mode, timer a4 controls the u phase and u phase, timer a1 ___ ___ controls the v phase and v phase, and timer a2 controls the w phase and w phase respectively; timer b2 controls the periods of one-shot pulse output from timers a4, a1, and a2. in outputting a waveform, dead time can be set so as to cause the l level of the positive waveform ___ output (u phase, v phase, and w phase) not to lap over the l level of the negative waveform output (u ___ ___ phase, v phase, and w phase). to set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. a value from 1 through 255 can be set as the count of the timer for setting dead time. the timer for setting dead time works as a one-shot timer. if a value is written to the dead timer (034c 16 ), the value is written to the reload register shared by the three timers for setting dead time. any of the timers for setting dead time takes the value of the reload register into its counter, if a start trigger comes from its corresponding timer, and performs a down count in line with the clock source selected by the dead time timer count source select bit (bit 2 at 0349 16 ). the timer can receive another trigger again before the workings due to the previous trigger are completed. in this instance, the timer performs a down count from the reload registers content after its transfer, provoked by the trigger, to the timer for setting dead time. since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger comes; it stops outputting pulses as soon as its content becomes 00 16 , and waits for the next trigger to come. ___ ___ the positive waveforms (u phase, v phase, and w phase) and the negative waveforms (u phase, v ___ phase, and w phase) in three-phase waveform mode are output from respective ports by means of setting 1 in the output control bit (bit 3 at 0348 16 ). setting 0 in this bit causes the ports to be the state of set by port direction register. this bit can be set to 0 not only by use of the applicable instruction, but _______ by entering a falling edge in the nmi terminal or by resetting. also, if 1 is set in the positive and negative phases concurrent l output disable function enable bit (bit 4 at 0348 16 ) causes one of the pairs of u ___ ___ ___ phase and u phase, v phase and v phase, and w phase and w phase concurrently go to l, as a result, the port become the state of set by port direction register.
105 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control timer b2 (timer mode) overflow interrupt occurrence frequency set counter interrupt request bit u(p8 0 ) u(p8 1 ) v(p7 2 ) v(p7 3 ) w(p7 4 ) w(p7 5 ) nmi reset r d d t q d t q d t q d t q for short circuit prevention d t q d t q q inv03 inv05 diagram for switching to p8 0 , p8 1 , and to p7 2 - p7 5 is not shown. inv04 timer a4 counter (one-shot timer mode) (one-shot timer mode) (one-shot timer mode) trigger timer a4 reload timer a4-1 timer a1 counter trigger timer a1 reload timer a1-1 timer a2 counter trigger timer a2 reload timer a2-1 inv0 7 t q inv11 dead time timer setting (8) inv00 1 0 inv01 inv11 du0 du1 t dq t dq dub0 dub1 t dq t dq u phase output control circuit u phase output signal u phase output signal v phase output control circuit to be set to ??when timer a4 stops t q inv11 to be set to ??when timer a1 stops t q inv11 to be set to ??when timer a2 stops u phase output control circuit v phase output signal w phase output signal v phase output signal w phase output signal signal to be written to b2 trigger signal for timer ai start trigger signal for transfer inv10 circuit foriinterrupt occurrence frequency set counter bit 0 at 034b 16 bit 0 at 034a 16 three-phase output shift register (u phase) control signal for timer a4 reload a f 1 inv12 1 1/2 n = 1 to 15 reload register n = 1 to 255 dead time timer setting n = 1 to 255 dead time timer setting (8) n = 1 to 255 n = 1 to 255 trigger inv06 trigger trigger trigger trigger trigger inv06 inv06 (note) note: to use three-phase output mode, write "1" to inv 12 . figure 1.18.5. block diagram for three-phase waveform mode
106 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control triangular wave modulation to generate a pwm waveform of triangular wave modulation, set 0 in the modulation mode select bit (bit 6 at 0348 16 ). also, set 1 in the timers a4-1, a1-1, a2-1 control bit (bit 1 at 0349 16 ). in this mode, each of timers a4, a1, and a2 has two timer registers, and alternately reloads the timer registers content to the counter every time timer b2 counters content becomes 0000 16 . if 1 is set to the effective interrupt output specification bit (bit 1 at 0348 16 ), the frequency of interrupt requests that occur every time the timer b2 counters value becomes 0000 16 can be set by use of the timer b2 counter (034d 16 ) for setting the frequency of interrupt occurrences. the frequency of occurrences is given by (setting; setting 0). setting 1 in the effective interrupt output specification bit (bit 1 at 0348 16 ) provides the means to choose which value of the timer a1 reload control signal to use, 0 or 1, to cause timer b2s interrupt request to occur. to make this selection, use the effective interrupt output polarity selection bit (bit 0 at 0348 16 ). an example of u phase waveform is shown in figure 1.18.6, and the description of waveform output workings is given below. set 1 in du0 (bit 0 at 034a 16 ). and set 0 in dub0 (bit 1 at 034a 16 ). in addition, set 0 in du1 (bit 0 at 034b 16 ) and set 1 in dub1 (bit 1 at 034b 16 ). also, set 0 in the effective interrupt output specification bit (bit 1 at 0348 16 ) to set a value in the timer b2 interrupt occurrence frequency set counter. by this setting, a timer b2 interrupt occurs when the timer b2 counters content becomes 0000 16 as many as (setting) times. furthermore, set 1 in the effective interrupt output specifi- cation bit (bit 1 at 0348 16 ), set in the effective interrupt polarity select bit (bit 0 at 0348 16 ) and set "1" in the interrupt occurrence frequency set counter(034d 16 ). these settings cause a timer b2 interrupt to occur every other interval when the u phase output goes to h. when the timer b2 counters content becomes 0000 16 , timer a4 starts outputting one-shot pulses. in this instance, the content of du1 (bit 0 at 034b 16 ) and that of du0 (bit 0 at 034a 16 ) are set in the three-phase output shift register (u phase), the content of dub1 (bit 1 at 034b 16 ) and that of dub0 (bit 1 at 034a 16 ) ___ are set in the three-phase shift register (u phase). after triangular wave modulation mode is selected, however, no setting is made in the shift register even though the timer b2 counters content becomes 0000 16 . ___ the value of du0 and that of dub0 are output to the u terminal (p8 0 ) and to the u terminal (p8 1 ) respectively. when the timer a4 counter counts the value written to timer a4 (038f 16 , 038e 16 ) and when timer a4 finishes outputting one-shot pulses, the three-phase shift registers content is shifted one posi- ___ tion, and the value of du1 and that of dub1 are output to the u phase output signal and to u phase output signal respectively. at this time, one-shot pulses are output from the timer for setting dead time used for ___ setting the time over which the l level of the u phase waveform does not lap over the l level of the u phase waveform, which has the opposite phase of the former. the u phase waveform output that started from the h level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift registers content changes from 1 to 0 by the effect of the one-shot pulses. when the timer for setting dead time finishes outputting one-shot pulses, "0" already shifted in the three-phase shift register goes effective, and the u phase waveform changes to the "l" level. when the timer b2 counters content becomes 0000 16 , the timer a4 counter starts counting the value written to timer a4-1 (0347 16 , 0346 16 ), and starts outputting one-shot pulses. when timer a4 fin- ishes outputting one-shot pulses, the three-phase shift registers content is shifted one position, but if the three-phase output shift registers content changes from 0 to 1 as a result of the shift, the output level changes from l to h without waiting for the timer for setting dead time to finish outputting one-shot pulses. a u phase waveform is generated by these workings repeatedly. with the exception that the three-phase output shift register on the u phase side is used, the workings in generating a u phase waveform, which has the opposite phase of the u phase waveform, are the same as in generating a u
107 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control timer a4 output trigger signal for timer ai start (timer b2 overflow signal) b2 u phase dead time a carrier wave of triangular waveform carrier wave signal wave timber b2 interrupt occurres rewriting timer a4 and timer a4-1. possible to set the number of overflows to generate an interrupt by use of the interrupt occurrences frequency set circuit u phase output signal m nn mp o note: set to triangular wave modulation mode and to three-phase mode 1. control signal for timer a4 reload m the three-phase shift register shifts in synchronization with the falling edge of the a4 output. u phase u phase output signal figure 1.18.6. timing chart of operation (1) phase waveform. in this way, a waveform can be picked up from the applicable terminal in a manner in which the "l" level of the u phase waveform doesnt lap over that of the u phase waveform, which has the opposite phase of the u phase waveform. the width of the l level too can be adjusted by varying the ___ ___ values of timer b2, timer a4, and timer a4-1. in dealing with the v and w phases, and v and w phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with ___ the u and u phases to generate an intended waveform.
108 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control figure 1.18.7. timing chart of operation (2) timer a4 output trigger signal for timer ai start (timer b2 overflow signal) timer b2 u phase dead time a carrier wave of triangular waveform carrier wave signal wave rewriting timer a4 every timer b2 interrupt occurres. u phase output signal m nn mp o note: set to triangular wave modulation mode and to three-phase mode 0. control signal for timer a4 reload m u phase u phase output signal timer b2 interrupt occurres. rewriting three-phase buffer register. assigning certain values to du0 (bit 0 at 034a 16 ) and dub0 (bit 1 at 034a 16 ), and to du1 (bit 0 at 034b 16 ) and dub1 (bit 1 at 034b 16 ) allows the user to output the waveforms as shown in figure 1.18.7, that is, to ___ ___ output the u phase alone, to fix u phase to h, to fix the u phase to h, or to output the u phase alone.
109 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control sawtooth modulation to generate a pwm waveform of sawtooth wave modulation, set 1 in the modulation mode select bit (bit 6 at 0348 16 ). also, set 0 in the timers a4-1, a1-1, and a2-1 control bit (bit 1 at 0349 16 ). in this mode, the timer registers of timers a4, a1, and a2 comprise conventional timers a4, a1, and a2 alone, and reload the corresponding timer registers content to the counter every time the timer b2 counters content be- comes 0000 16 . the effective interrupt output specification bit (bit 1 at 0348 16 ) and the effective interrupt output polarity select bit (bit 0 at 0348 16 ) go nullified. an example of u phase waveform is shown in figure 75, and the description of waveform output workings is given below. set 1 in du0 (bit 0 at 034a 16 ), and set 0 in dub0 (bit 1 at 034a 16 ). in addition, set 0 in du1 (bit 0 at 034a 16 ) and set 1 in dub1 (bit 1 at 034a 16 ). when the timber b2 counters content becomes 0000 16 , timer b2 generates an interrupt, and timer a4 starts outputting one-shot pulses at the same time. in this instance, the contents of the three-phase buffer registers du1 and du0 are set in the three-phase output shift register (u phase), and the contents of dub1 and dub0 are set in the three-phase output register (u phase). after this, the three-phase buffer registers content is set in the three-phase shift register every time the timer b2 counters content be- comes 0000 16 . ___ the value of du0 and that of dub0 are output to the u terminal (p8 0 ) and to the u terminal (p8 1 ) respectively. when the timer a4 counter counts the value written to timer a4 (038f 16 , 038e 16 ) and when timer a4 finishes outputting one-shot pulses, the three-phase output shift registers content is shifted one ___ position, and the value of du1 and that of dub1 are output to the u phase output signal and to the u output signal respectively. at this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the l level of the u phase waveform doesnt lap over the l level of ___ the u phase waveform, which has the opposite phase of the former. the u phase waveform output that started from the h level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift registers content changes from 1 to 0 by the effect of the one-shot pulses. when the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and the u phase waveform changes to the l level. when the timer b2 counters content becomes 0000 16 , the contents of the three-phase buffer registers du1 and du0 are set in the three-phase shift register (u phase), and the contents of dub1 and ___ dub0 are set in the three-phase shift register (u phase) again. a u phase waveform is generated by these workings repeatedly. with the exception that the three-phase ___ ___ output shift register on the u phase side is used, the workings in generating a u phase waveform, which has the opposite phase of the u phase waveform, are the same as in generating a u phase waveform. in this way, a waveform can be picked up from the applicable terminal in a manner in which the l level of the u phase waveform doesnt lap over that of the u phase waveform, which has the opposite phase of the u phase waveform. the width of the l level too can be adjusted by varying the values of timer b2 ___ ___ and timer a4. in dealing with the v and w phases, and v and w phases, the latter are of opposite phase ___ of the former, have the corresponding timers work similarly to dealing with the u and u phases to gener- ate an intended waveform. ___ setting 1 both in dub0 and in dub1 provides a means to output the u phase alone and to fix the u phase output to h as shown in figure 1.18.8.
110 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control timer b2 timer a4 output u phase u phase dead time carrier wave signal wave a carrier wave of sawtooth waveform m n o p note: set to sawtooth modulation mode and to three-phase mode 0. interrupt occurres. rewriting the value of timer a4. u phase output signal u phase output signal the three-phase shift register shifts in synchronization with the falling edge of timer a4. data transfer is made from the three- phase buffer register to the three- phase shift register in step with the timing of the timer b overflow. trigger signal for timer ai start (timer b2 overflow signal) figure 1.18.8. timing chart of operation (3)
111 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development timers functions for three-phase motor control timer b2 timer a4 output u phase u phase dead time carrier wave signal wave a carrier wave of sawtooth waveform mn p note: set to sawtooth modulation mode and to three-phase mode 0. u phase output signal u phase output signal the three-phase shift register shifts in synchronization with the falling edge of timer a4. trigger signal for timer ai start (timer b2 overflow signal) interrupt occurres. rewriting the value of timer a4. rewriting three-phase output buffer register data transfer is made from the three- phase buffer register to the three- phase shift register in step with the timing of the timer b overflow. interrupt occurres. rewriting the value of timer a4. figure 1.18.9. timing chart of operation (4)
112 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development serial i/o serial i/o serial i/o is configured as five channels: uart0, uart1, uart2, s i/o3 and s i/o4. uart0 to 2 uart0, uart1 and uart2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 1.19.1 shows the block diagram of uart0, uart1 and uart2. figures 1.19.2 and 1.19.3 show the block diagram of the transmit/receive unit. uarti (i = 0 to 2) has two operation modes: a clock synchronous serial i/o mode and a clock asynchronous serial i/o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 03a0 16 , 03a8 16 and 0378 16 ) determine whether uarti is used as a clock synchronous serial i/o or as a uart. although a few functions are different, uart0, uart1 and uart2 have almost the same functions. uart0 through uart2 are almost equal in their functions with minor exceptions. uart2, in particular, is compliant with the sim interface with some extra settings added in clock-asynchronous serial i/o mode (note). it also has the bus collision detection function that generates an interrupt request if the txd pin and the rxd pin are different in level. in m30623(80-pin package), uart2 has the clock-asynchronous serial i/o mode and iic mode. table 1.19.1 shows the comparison of functions of uart0 through uart2, and figures 1.19.4 to 1.19.8 show the registers related to uarti. note: sim : subscriber identity module table 1.19.1. comparison of functions of uart0 through uart2 note 1: only when clock synchronous serial i/o mode. note 2: only when clock synchronous serial i/o mode and 8-bit uart mode. note 3: only when uart mode. note 4: using for sim interface. note 5: in m30623(80-pin package), do not use this function, because clk 2 and cts 2 /rts 2 have no external pin. note 6: connect via pull-up resistor to v cc outside. note 7: generally, it use in case of ie bus-emulation. uart0 uart1 uart2 function clk polarity selection continuous receive mode selection lsb first / msb first selection impossible transfer clock output from multiple pins selection impossible impossible impossible impossible serial data logic switch impossible sleep mode selection impossible impossible txd, rxd i/o polarity switch impossible possible cmos output txd, rxd port output format cmos output n-channel open-drain output (note 6) impossible parity error signal output impossible impossible bus collision detection impossible possible (note 7) possible (note 1) separate cts/rts pins possible (note 1) possible (note 1) possible (note 3) possible (note 1) possible (note 1) possible (note 1) possible (note 1) possible (note 3) possible possible (note 1) possible (note 2) possible (note 1) possible (note 4) possible (note 4) impossible (note 5) m30623 (80pin-package) m30622 (100pin-package)
113 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development serial i/o figure 1.19.1. block diagram of uarti (i = 0 to 2) n0 : values set to uart0 bit rate generator (brg0) n1 : values set to uart1 bit rate generator (brg1) n2 : values set to uart2 bit rate generator (brg2) rxd 2 reception control circuit transmission control circuit 1 / (n 2 +1) 1/16 1/16 1/2 bit rate generator (address 0379 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 2 cts 2 / rts 2 f 1 f 8 f 32 vcc rts 2 cts 2 txd 2 (uart2) rxd polarity reversing circuit txd polarity reversing circuit rxd 0 1 / (n 0 +1) 1/2 bit rate generator (address 03a1 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 0 clock source selection cts 0 / rts 0 f 1 f 8 f 32 reception control circuit transmission control circuit internal external vcc rts 0 cts 0 txd 0 transmit/ receive unit rxd 1 1 / (n 1 +1) 1/16 1/16 1/2 bit rate generator (address 03a9 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 1 clock source selection f 1 f 8 f 32 reception control circuit transmission control circuit internal external rts 1 cts 1 txd 1 (uart1) (uart0) clk polarity reversing circuit clk polarity reversing circuit cts/rts disabled cts/rts separated clock output pin select switch cts 1 / rts 1 / cts 0 / clks 1 cts/rts disabled cts0 from uart1 cts/rts selected cts/rts disabled v cc cts0 to uart0 cts 0 cts/rts disabled cts/rts separated cts/rts disabled cts/rts disabled cts/rts selected clk polarity reversing circuit internal external clock source selection transmit/ receive unit transmit/ receive unit 1/16 1/16 note 1: in m30623(80-pin package), clk 2 and cts 2 /rts 2 have no external pin. note 2: in m30623(80-pin package), do not use uart2 as clock synchronous serial i/o.
114 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development serial i/o figure 1.19.2. block diagram of uarti (i = 0, 1) transmit/receive unit sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03ae 16 address 03af 16 address 03a2 16 address 03a3 16 address 03aa 16 address 03ab 16 data bus low-order bits msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? data bus high-order bits
115 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development serial i/o sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txd2 uart2 transmit register par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart2 transmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uart2 receive buffer register uart2 receive register 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxd2 uart (8 bits) uart (9 bits) address 037e 16 address 037f 16 address 037a 16 address 037b 16 data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? reverse no reverse error signal output circuit rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp: stop bit par: parity bit note 1: in m30623(80-pin package), do not use uart2 as clock synchronous serial i/o. figure 1.19.3. block diagram of uart2 transmit/receive unit
116 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development serial i/o figure 1.19.4. serial i/o-related registers (1) b7 uarti bit rate generator b0 symbol address when reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate u2brg 0379 16 indeterminate function assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmit data nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turn out to be indeterminate. symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u1tb 03ab 16 , 03aa 16 indeterminate u2tb 037b 16 , 037a 16 indeterminate w r (b15) symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u1rb 03af 16 , 03ae 16 indeterminate u2rb 037f 16 , 037e 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note 1: bits 15 through 12 are set to 0 when the serial i/o mode select bit (bits 2 to 0 at addresses 03a0 16 , 03a8 16 and 0378 16 ) are set to 000 2 or the receive enable bit is set to 0. (bit 15 is set to 0 when bits 14 to 12 all are set to 0.) bits 14 and 13 are also set to 0 when the lower byte of the uarti receive buffer register (addresses 03a6 16 , 03ae 16 and 037e 16 ) is read out. note 2: arbitration lost detecting flag is allocated to u2rb and noting but 0 may be written. nothing is assigned in bit 11 of u0rb and u1rb. these bits can neither be set or reset. when read, the value of this bit is 0. invalid invalid invalid oer fer per sum overrun error flag (note 1) framing error flag (note 1) parity error flag (note 1) error sum flag (note 1) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. receive data w r receive data abt arbitration lost detecting flag (note 2) invalid 0 : not detected 1 : detected
117 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development serial i/o uarti transmit/receive mode register symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye slep parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit sleep select bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = ? 0 : odd parity 1 : even parity invalid invalid must always be ? function (during uart mode) function (during clock synchronous serial i/o mode) uart2 transmit/receive mode register symbol address when reset u2mr 0378 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : (note) 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse usually set to ? 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = ? 0 : odd parity 1 : even parity invalid invalid 0 : no reverse 1 : reverse usually set to ? function (during uart mode) function (during clock synchronous serial i/o mode) a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a note 1: bit 2 to bit 0 are set to 010 2 when iic mode is used. note 2: in m30623(80-pin package), do not select the external clock, because there is no external pin. note 3: in m30623(80-pin package), do not use uart2 as clock synchronous serial i/o. (note 3) (note 2) figure 1.19.5. serial i/o-related registers (2)
118 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development serial i/o uarti transmit/receive control register 0 symbol address when reset uic0(i=0,1) 03a4 16 , 03ac 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit data output select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be ? bit name bit symbol must always be ? note 1: set the corresponding port direction register to ?? note 2: the settings of the corresponding port register and port direction register are invalid. 0 : cts/rts function enabled 1 : cts/rts function disabled (p6 0 and p6 4 function as programmable i/o port) aa a aa a aa a aa aa a aa a aa aa a a aa aa a a uart2 transmit/receive control register 0 symbol address when reset u2c0 037c 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit (note 3) 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be 0 bit name bit symbol note 1: set the corresponding port direction register to 0. note 2: the settings of the corresponding port register and port direction register are invalid. note 3: only clock synchronous serial i/o mode and 8-bit uart mode are valid. note 4: in m30623(80-pin package), these bits are invalid, because clk 2 and cts 2 /rts 2 have no external pin. note 5: in m30623(80-pin package), do not use uart2 as clock synchronous serial i/o. 0 : cts/rts function enabled 1 : cts/rts function disabled (p7 3 functions programmable i/o port) nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be 0. 0 : lsb first 1 : msb first aa a aa a aa a aa aa a aa aa a a aa aa a a (note 5) (note 4) (note 4) (note 4) figure 1.19.6. serial i/o-related registers (3)
119 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development serial i/o figure 1.19.7. serial i/o-related registers (4) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 03a5 16 , 03ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? uart2 transmit/receive control register 1 symbol address when reset u2c1 037d 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register u2irs uart2 transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) u2rrm uart2 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled invalid data logic select bit 0 : no reverse 1 : reverse 0 : no reverse 1 : reverse u2lch u2ere error signal output enable bit must be fixed to ? 0 : output disabled 1 : output enabled aa a aa aa a aa a aa aa a a aa a aa a aa a aa aa a a aa aa aa note 1: in m30623(80-pin package), do not use uart2 as clock synchronous serial i/o. (note 1)
120 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development serial i/o note: when using multiple pins to output the transfer clock, the following requirements must be met: ?uart1 internal/external clock select bit (bit 3 at address 03a8 16 ) = ?? uart transmit/receive control register 2 symbol address when reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 rcsp uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : normal mode (clk output is clk1 only) 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate. 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) must always be ? u0irs u1irs u0rrm u1rrm 0 : cts/rts shared pin 1 : cts/rts separated 0 : cts/rts shared pin 1 : cts/rts separated separate cts/rts bit invalid invalid invalid clk/clks select bit 1 (note) valid when bit 5 = ?? 0 : clock output to clk1 1 : clock output to clks1 a aa a aa a a aa aa a aa a aa a aa a aa uart2 special mode register symbol address when reset u2smr 0377 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) abscs acse sss iic mode selection bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : normal mode 1 : iic mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : ordinary 1 : falling edge of rxd2 0 : disabled 1 : enabled transmit start condition select bit must always be 0 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit aa aa a a aa a a a a a a a a a aa a aa aa a a 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be 0. (note 2) note 1: in m30623(80-pin package), do not use uart2 as clock synchronous serial i/o. note 2: nothing but "0" may be written. (note 1) figure 1.19.8. serial i/o-related registers (5)
121 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock synchronous serial i/o mode item specification transfer data format ? transfer data length: 8 bits transfer clock ? when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 0) : fi/ 2(n+1) (note 1) fi = f 1 , f 8 , f 32 ? when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 1) : input from clki pin transmission/reception control _______ _______ _______ _______ ? cts function/ rts function/ cts , rts function chosen to be invalid transmission start condition ? to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 _______ _______ _ when cts function selected, cts input level = l ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 1: clki input level = l reception start condition ? to start reception, the following requirements must be met: _ receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 _ transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 1: clki input level = l ? when transmitting _ transmit interrupt cause select bit (bits 0, 1 at address 03b0 16 , bit 4 at address 037d 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed _ transmit interrupt cause select bit (bits 0, 1 at address 03b0 16 , bit 4 at address 037d 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving _ interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ? overrun error (note 2) this error occurs when the next data is ready before contents of uarti receive buffer register are read out interrupt request generation timing note 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. note 2: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. tables 1.19.2 and 1.19.3 list the specifications of the clock synchronous serial i/o mode. figure 1.19.9 shows the uarti transmit/receive mode register. in m30623(80-pin package), do not use uart2 as clock synchronous serial i/o. table 1.19.2. specifications of clock synchronous serial i/o mode (1)
122 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock synchronous serial i/o mode item specification select function ? clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register ? transfer clock output from multiple pins selection (uart1) (note) uart1 transfer clock can be chosen by software to be output from one of the two pins set _______ _______ ? separate cts/rts pins (uart0) (note) _______ _______ uart0 cts and rts pins each can be assigned to separate pins ? switching serial data logic (uart2) whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. ? txd, rxd i/o polarity reverse (uart2) this function is reversing txd port output and rxd port input. all i/o data level is reversed. table 1.19.4. specifications of clock synchronous serial i/o mode (2) _______ _______ note: the transfer clock output from multiple pins and the separate cts/rts pins functions cannot be selected simultaneously.
123 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock synchronous serial i/o mode figure 1.19.9. uarti transmit/receive mode register in clock synchronous serial i/o mode symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit/receive mode registers internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be ??in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit/receive mode register internal/external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode txd, rxd i/o polarity reverse bit (note) 0 : no reverse 1 : reverse note: usually set to ?? a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
124 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock synchronous serial i/o mode table 1.19.4 lists the functions of the input/output pins during clock synchronous serial i/o mode. this _______ table shows the pin functions when the transfer clock output from multiple pins and the separate cts/ _______ rts pins functions are not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n-channel open-drain is selected, this pin is in floating state.) table 1.19.4. input/output pin functions in clock synchronous serial i/o mode pin name function method of selection txdi (p6 3 , p6 7 , p7 0 ) serial data output serial data input transfer clock output transfer clock input programmable i/o port (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = ? internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = ? port p6 1 , p6 5 and p7 2 direction register (bits 1 and 5 at address 03ee 16 , bit 2 at address 03ef 16 ) = ? port p6 2 , p6 6 and p7 1 direction register (bits 2 and 6 at address 03ee 16 , bit 1 at address 03ef 16 )= ?? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) =?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ?? port p6 0 , p6 4 and p7 3 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16) = ?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) _______ _______ (when transfer clock output from multiple pins and separate cts/rts pins functions are not selected)
125 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock synchronous serial i/o mode figure 1.19.10. typical transmit/receive timings in clock synchronous serial i/o mode ? example of transmit timing (when internal clock is selected) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk stopped pulsing because transfer enable bit = 0 data is set in uarti transmit buffer register tc = tclk = 2(n + 1) / fi fi: frequency of brgi count source (f 1 , f 8 , f 32 ) n: value set to brgi transfer clock transmit enable bit (te) transmit buffer empty flag (tl) clki txdi transmit register empty flag (txept) h l 0 1 0 1 0 1 ctsi the above timing applies to the following settings: ? internal clock is selected. ? cts function is selected. ? clk polarity select bit = 0. ? transmit interru p t cause select bit = 0 transmit interrupt request bit (ir) 0 1 stopped pulsing because cts = h transferred from uarti transmit buffer register to uarti transmit register shown in ( ) are bit symbols. cleared to 0 when interrupt request is accepted, or cleared by software 1 / f ext dummy data is set in uarti transmit buffer register transmit enable bit (te) transmit buffer empty flag (tl) clki rxdi receive complete flag (rl) rtsi h l 0 1 0 1 0 1 receive enable bit (re) 0 1 receive data is taken in transferred from uarti transmit buffer register to uarti transmit register read out from uarti receive buffer register the above timing applies to the following settings: ? external clock is selected. ? rts function is selected. ? clk polarity select bit = 0. f ext : frequency of external clock transferred from uarti receive register to uarti receive buffer register receive interrupt request bit (ir) 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 shown in ( ) are bit symbols. cleared to 0 when interrupt request is accepted, or cleared by software meet the following conditions are met when the clk input before data reception = h ? transmit enable bit 1 ? receive enable bit 1 ? dummy data write to uarti transmit buffer register ? example of receive timing (when external clock is selected)
126 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock synchronous serial i/o mode (a) polarity select function as shown in figure 1.19.11, the clk polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 , 037c 16 ) allows selection of the polarity of the transfer clock. ?when clk polarity select bit = ? note 2: the clk pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i ?when clk polarity select bit = ? note 1: the clk pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i figure 1.19.11. polarity of transfer clock (b) lsb first/msb first select function as shown in figure 1.19.12, when the transfer format select bit (bit 7 at addresses 03a4 16 , 03ac 16 , 037c 16 ) = 0, the transfer format is lsb first; when the bit = 1, the transfer format is msb first. figure 1.19.12. transfer format lsb first ?when transfer format select bit = ? d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i ?when transfer format select bit = ? d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i msb first note: this applies when the clk polarity select bit = ??
127 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock synchronous serial i/o mode (c) transfer clock output from multiple pins function (uart1) this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the clk and clks select bit (bits 4 and 5 at address 03b0 16 ). (see figure 1.19.3.) the multiple pins function is valid only when the internal clock is selected for uart1. note that when _______ _______ this function is selected, uart1 cts/rts function cannot be used. figure 1.19.13. the transfer clock output from the multiple pins function usage microcomputer t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 ) in clk in clk note: this applies when the internal clock is selected and transmission is performed only in clock synchronous serial i/o mode. (d) continuous receive mode if the continuous receive mode enable bit (bits 2 and 3 at address 03b0 16 , bit 5 at address 037d 16 ) is set to 1, the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. _______ _______ (e) separate cts/rts pins function (uart0) this function works the same way as in the clock asynchronous serial i/o (uart) mode. the method of setting and the input/output pin functions are both the same, so refer to select function in the next section, (2) clock asynchronous serial i/o (uart) mode. note that this function is invalid if the transfer clock output from the multiple pins function is selected. (f) serial data logic switch function (uart2) when the data logic select bit (bit6 at address 037d 16 ) = 1, and writing to transmit buffer register or reading from receive buffer register, data is reversed. figure 1.19.14 shows the example of serial data logic switch timing. figure 1.19.14. serial data logic switch timing d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd 2 (no reverse) txd 2 (reverse) ? ? ? ? ? ? ?hen lsb first
128 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock asynchronous serial i/o (uart) mode item specification transfer data format ? character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected ? start bit: 1 bit ? parity bit: odd, even, or nothing as selected ? stop bit: 1 bit or 2 bits as selected transfer clock ? when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 = 0) : fi/16(n+1) (note 1) fi = f 1 , f 8 , f 32 ? when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 , 0378 16 =1) : f ext /16(n+1) (note 1) (note 2) transmission/reception control _______ _______ _______ _______ ? cts function/rts function/cts, rts function chosen to be invalid (note 4) transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 - transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 0 _______ _______ - when cts function selected, cts input level = l (note 4) reception start condition ? to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 , 037d 16 ) = 1 - start bit detection interrupt request ? when transmitting generation timing - t ransmit interrupt cause select bits (bits 0,1 at address 03b0 16 , bit4 at address 037d 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0, 1 at address 03b0 16 , bit4 at address 037d 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1s in parity and character bits does not match the number of 1s set ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered (2) clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 1.19.5 and 1.19.6 list the specifications of the uart mode. figure 1.19.15 shows the uarti transmit/receive mode register. table 1.19.5. specifications of uart mode (1) note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clki pin. in m30623(80-pin package), do not select the external clock as transfer clock, because there is no external pin of clk 2 . note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. ________ ________ note 4: in m30623(80-pin package), do not use these functions, because there is no external pin of cts 2 /rts 2 .
129 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock asynchronous serial i/o (uart) mode table 1.19.6. specifications of uart mode (2) item specification select function _______ _______ ? separate cts/rts pins (uart0) _______ _______ uart0 cts and rts pins each can be assigned to separate pins ? sleep mode selection (uart0, uart1) this mode is used to transfer data to and from one of multiple slave micro- computers ? serial data logic switch (uart2) this function is reversing logic value of transferring data. start bit, parity bit and stop bit are not reversed. ?t x d, r x d i/o polarity switch this function is reversing t x d port output and r x d port input. all i/o data level is reversed.
130 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock asynchronous serial i/o (uart) mode figure 1.19.15. uarti transmit/receive mode register in uart mode symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit / receive mode registers internal / external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit sleep select bit symbol address when reset u2mr 0378 16 00 16 ckdir uart2 transmit / receive mode register internal / external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock (note 2) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit txd, rxd i/o polarity reverse bit (note 1) a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a note 1: usually set to 0. note 2: in m30623(80-pin package), do not select the external clock as transfer clock, because there is no external pin of clk 2 .
131 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock asynchronous serial i/o (uart) mode table 1.19.7 lists the functions of the input/output pins during uart mode. this table shows the pin _______ _______ functions when the separate cts/rts pins function is not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n-channel open-drain is selected, this pin is in floating state.) table 1.19.7. input/output pin functions in uart mode pin name function method of selection txdi (p6 3 , p6 7 , p7 0 ) serial data output serial data input programmable i/o port transfer clock input programmable i/o port rxdi (p6 2 , p6 6 , p7 1 ) clki (p6 1 , p6 5 , p7 2 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = ? internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 , 0378 16 ) = ?? port p6 1 , p6 5 and p7 2 direction register (bits 1 and 5 at address 03ee 16 , bit 2 at address 03ef 16 ) = ? port p6 2 , p6 6 and p7 1 direction register (bits 2 and 6 at address 03ee 16 , bit 1 at address 03ef 16 )= ?? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) =?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ?? port p6 0 , p6 4 and p7 3 direction register (bits 0 and 4 at address 03ee 16 , bit 3 at address 03ef 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16) = ?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 , 037c 16 ) = ? cts input rts output ctsi/rtsi (p6 0 , p6 4 , p7 3 ) (note 1) (note 2) ________ _______ (when separate cts/rts pins function is not selected) note 1: in m30623(80-pin package), use the internal clock as transfer clock of uart2, because there is no external pin of clk 2 (p7 2 ). note 2: in m30623(80-pin package), uart2 does not have these functions, because there is no external pin ________ _______ of cts 2 /rts 2 (p7 3 ).
132 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock asynchronous serial i/o (uart) mode transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) start bit parity bit txdi ctsi the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?cts function is selected. ?transmit interrupt cause select bit = ?? ? ? ? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? cleared to ??when interrupt request is accepted, or cleared by software transmit enable bit(te) transmit buffer empty flag(ti) txdi transmit register empty flag (txept) ? ? ? ? ? ? the above timing applies to the following settings : ?parity is disabled. ?two stop bits. ?cts function is disabled. ?transmit interrupt cause select bit = ?? transfer clock tc tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? shown in ( ) are bit symbols. shown in ( ) are bit symbols. tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stopped pulsing because transmit enable bit = ? stop bit transferred from uarti transmit buffer register to uarti transmit register start bit the transfer clock stops momentarily as cts is ??when the stop bit is checked. the transfer clock starts as the transfer starts immediately cts changes to ?? data is set in uarti transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp transferred from uarti transmit buffer register to uarti transmit register stop bit stop bit data is set in uarti transmit buffer register. ? sp cleared to ??when interrupt request is accepted, or cleared by software note 1: in m30623(80-pin package), there is no external pin of cts 2 , so do not use the function using this pin. ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ? example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) figure 1.19.16. typical transmit timings in uart mode
133 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock asynchronous serial i/o (uart) mode ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure 1.19.17. typical receive timing in uart mode _______ _______ (a) separate cts/rts pins function (uart0) _______ _______ _______ setting the cts/rts separate bit (bit 6 of address 03b0 16 ) to "1" inputs/outputs the cts signal and _______ _______ _______ _______ _______ rts signal from different pins. choose which to use, cts or rts, by use of the cts/rts function select bit (bit 2 of address 03a4 16 ). this function is effective in uart0 only. with this function cho- _______ _______ _______ _______ sen, the user cannot use the cts/rts function. set "0" both to the cts/rts function select bit (bit _______ _______ 2 of address 03ac 16 ) and to the cts/rts disable bit (bit 4 of address 03ac 16 ). (b) sleep mode (uart0, uart1) this mode is used to transfer data between specific microcomputers among multiple microcomputers connected using uarti. the sleep mode is selected when the sleep select bit (bit 7 at addresses 03a0 16 , 03a8 16 ) is set to 1 during reception. in this mode, the unit performs receive operation when the msb of the received data = 1 and does not perform receive operation when the msb = 0. d 0 start bit sampled l receive data taken in brgi count source receive enable bit rxdi transfer clock receive complete flag rtsi stop bit 1 0 0 1 h l the above timing applies to the following settings : ?parity is disabled. ?one stop bit. ?rts function is selected. receive interrupt request bit 0 1 transferred from uarti receive register to uarti receive buffer register reception triggered when transfer clock is generated by falling edge of start bit d 7 d 1 cleared to 0 when interrupt request is accepted, or cleared by software note 1: in m30623 ( 80-pin packa g e ), there is no external pin of rts 2 , so do not use the function usin g this pin. _______ _______ figure 1.19.18. the separate cts/rts pins function usage microcomputer t x d 0 (p6 3 ) r x d 0 (p6 2 ) in out cts rts cts0 (p6 4 ) rts0 (p6 0 ) ic note : the user cannot use cts and rts at the same time.
134 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock asynchronous serial i/o (uart) mode (c) function for switching serial data logic (uart2) when the data logic select bit (bit 6 of address 037d 16 ) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. figure 1.19.19 shows the ex- ample of timing for switching serial data logic. figure 1.19.19. timing for switching serial data logic, and i/o polarity reverse st : start bit p : even parity sp : stop bit transfer clock ? ? d0 d1 d2 d3 d4 d5 d6 d7 p sp st ? ? sp st d3 d4 d5 d6 d7 p d0 d1 d2 ? ? ?when lsb first, parity enabled, one stop bit no logic reverse no polarity reverse txd 2 logic reverse no polarity reverse txd 2 logic reverse polarity reverse txd 2 no logic reverse polarity reverse txd 2 sp st d3 d4 d5 d6 d7 p d0 d1 d2 ? ? d0 d1 d2 d3 d4 d5 d6 d7 p sp st ? ? (d) txd, rxd i/o polarity reverse function (uart2) this function is to reverse t x d pin output and r x d pin input. the level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. set this function to 0 (not to reverse) for usual use. figure 1.19.19 shows the example of timing for i/o polarity reverse. (e) bus collision detection function (uart2) this function is to sample the output level of the t x d pin and the input level of the r x d pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. figure 1.19.20 shows the example of detection timing of a buss collision (in uart mode). figure 1.19.20. detection timing of a bus collision (in uart mode) st : start bit sp : stop bit st st sp sp transfer clock txd 2 rxd 2 bus collision detection interrupt request signal ? ? ? ? ? ? ? ? bus collision detection interrupt request bit ? ?
135 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock asynchronous serial i/o (uart) mode item specification transfer data format ? transfer data 8-bit uart mode (bit 2 through bit 0 of address 0378 16 = 101 2 ) ? one stop bit (bit 4 of address 0378 16 = 0) ? with the direct format chosen set parity to even (bit 5 and bit 6 of address 0378 16 = 1 and 1 respectively) set data logic to direct (bit 6 of address 037d 16 = 0). set transfer format to lsb (bit 7 of address 037c 16 = 0). ? with the inverse format chosen set parity to odd (bit 5 and bit 6 of address 0378 16 = 0 and 1 respectively) set data logic to inverse (bit 6 of address 037d 16 = 1) set transfer format to msb (bit 7 of address 037c 16 = 1) transfer clock ? with the internal clock chosen (bit 3 of address 0378 16 = 0) : fi / 16 (n + 1) (note 1) : fi=f 1 , f 8 , f 32 ? with an external clock chosen (bit 3 of address 0378 16 = 1) : f ext / 16 (n+1) (note 1) (note 2) transmission / reception control _______ _______ ? disable the cts and rts function (bit 4 of address 037c 16 = 1) other settings ? the sleep mode select function is not available for uart2 ? set transmission interrupt factor to transmission completed (bit 4 of address 037d 16 = 1) transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 of address 037d 16 ) = 1 - transmit buffer empty flag (bit 1 of address 037d 16 ) = 0 r eceptio n start condition ? to start reception, the following requirements must be met: - reception enable bit (bit 2 of address 037d 16 ) = 1 - detection of a start bit ? when transmitting when data transmission from the uart2 transfer register is completed (bit 4 of address 037d 16 = 1) ? when receiving when data transfer from the uart2 receive register to the uart2 receive buffer register is completed error detection ? overrun error (see the specifications of clock-asynchronous serial i/o) (note 3) ? framing error (see the specifications of clock-asynchronous serial i/o) ? parity error (see the specifications of clock-asynchronous serial i/o) - on the reception side, an l level is output from the t x d 2 pin by use of the parity error signal output function (bit 7 of address 037d 16 = 1) when a parity error is detected - on the transmission side, a parity error is detected by the level of input to the r x d 2 pin when a transmission interrupt occurs ? the error sum flag (see the specifications of clock-asynchronous serial i/o) (3) clock-asynchronous serial i/o mode (compliant with the sim interface) the sim interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in uart2 clock-asynchronous serial i/o mode allows the user to effect this function. table 1.19.8 shows the specifications of clock-asynchronous serial i/o mode (compliant with the sim interface). interrupt request generation timing note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clk 2 pin. in m30623(80-pin package), do not select the external clock as transfer clock of uart2, because there is no external pin of clk 2 . note 3: if an overrun error occurs, the uart2 receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. table 1.19.8. specifications of clock-asynchronous serial i/o mode (compliant with the sim interface)
136 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock asynchronous serial i/o (uart) mode figure 1.19.21. typical transmit/receive timing in uart mode (compliant with the sim interface) transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? ? ? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p shown in ( ) are bit symbols. tc transfer clock sp stop bit data is set in uarti transmit buffer register sp a ??level returns from txd 2 due to the occurrence of a parity error. the level is detected by the interrupt routine. the level is detected by the interrupt routine. receive enable bit (re) receive complete flag (ri) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit txd 2 the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi receive interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp shown in ( ) are bit symbols. tc transfer clock sp stop bit a ??level returns from txd 2 due to the occurrence of a parity error. rxd 2 read to receive buffer read to receive buffer d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p signal conductor level (note 1) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp txd 2 rxd 2 signal conductor level (note 1) note: equal in waveform because txd 2 and rxd 2 are connected. transferred from uarti transmit buffer register to uarti transmit register cleared to ??when interrupt request is accepted, or cleared by software cleared to ??when interrupt request is accepted, or cleared by software
137 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock asynchronous serial i/o (uart) mode (a) function for outputting a parity error signal with the error signal output enable bit (bit 7 of address 037d 16 ) assigned 1, you can output an l level from the txd 2 pin when a parity error is detected. in step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. figure 1.19.22 shows the output timing of the parity error signal. figure 1.19.22. output timing of the parity error signal st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st hi-z transfer clock rxd 2 txd 2 receive complete flag ? ? ? ? ? ? ? ?lsb first ? (b) direct format/inverse format connecting the sim card allows you to switch between direct format and inverse format. if you choose the direct format, d 0 data is output from txd 2 . if you choose the inverse format, d 7 data is inverted and output from txd 2 . figure 1.19.23 shows the sim interface format. figure 1.19.23. sim interface format p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p transfer clcck txd 2 (direct) txd 2 (inverse) d7 d6 d5 d4 d3 d2 d1 d0 p
138 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development clock asynchronous serial i/o (uart) mode figure 1.19.24 shows the example of connecting the sim interface. connect t x d 2 and r x d 2 and apply pull-up. figure 1.19.24. connecting the sim interface microcomputer sim card txd 2 rxd 2
139 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development uart2 special mode register uart2 special mode register the uart2 special mode register (address 0377 16 ) is used to control uart2 in various ways. figure 1.19.25 shows the uart2 special mode register. uart2 special mode register symbol address when reset u2smr 0377 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) abscs acse sss iic mode selection bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : normal mode 1 : iic mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : ordinary 1 : falling edge of rxd2 0 : disabled 1 : enabled transmit start condition select bit must always be ? 0 : rising edge of transfer clock 1 : underflow signal of timer a0 auto clear function select bit of transmit enable bit a a aa aa a aa a a aa aa a aa a a aa aa a aa a a aa aa 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 nothing is assigned. in an attempt to write to this bit, write 0. the value, if read, turns out to be 0. note: nothing but "0" may be written. (note) figure 1.19.25. uart2 special mode register function normal mode iic mode (note 1) factor of interrupt number 15 (note 2) uart2 transmission no acknowledgment detection (nack) factor of interrupt number 16 (note 2) uart2 reception start condition detection or stop condition detection uart2 transmission output delay not delayed delayed p7 0 at the time when uart2 is in use txd 2 (output) sda (input/output) (note 3) p7 1 at the time when uart2 is in use rxd 2 (input) scl (input/output) p7 2 at the time when uart2 is in use (note 4) clk 2 p7 2 dma1 factor at the time when 1 1 0 1 is assigned to the dma request factor selection bits uart2 reception acknowledgment detection (ack) noise filter width 15ns 50ns reading p7 1 reading the terminal when 0 is assigned to the direction register reading the terminal regardless of the value of the direction register 1 2 3 4 5 6 7 8 9 note 1: make the settings given below when iic mode is in use. set 0 1 0 in bits 2, 1, 0 of the uart2 transmission/reception mode register. disable the rts/cts function. choose the lsb first function. note 2: follow the steps given below to switch from a factor to another. 1. disable the interrupt of the corresponding number. 2. switch from a factor to another. 3. reset the interrupt request flag of the corresponding number. 4. set an interrupt level of the corresponding number. note 3: set an initial value of sda transmission output when serial i/o is invalid. note 4: in m30623(80-pin package), p7 2 is not connected to external pin. factor of interrupt number 10 (note 2) bus collision detection acknowledgment detection (ack) 10 initial value of uart2 output h level (when 0 is assigned to the clk polarity select bit) the value set in latch p7 0 when the port is selected 11 table 1.19.9. features in iic mode
140 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development uart2 special mode register figure 1.19.26 shows the functional block diagram for iic mode. setting 1 in the iic mode selection bit (iicm) causes ports p7 0 , p7 1 , and p7 2 to work as data transmission-reception terminal sda, clock input- output terminal scl, and port p7 2 respectively. a delay circuit is added to the sda transmission output, so the sda output changes after scl fully goes to l. an attempt to read port p7 1 (scl) results in getting the terminals level regardless of the content of the port direction register. the initial value of sda transmission output in this mode goes to the value set in port p7 0 . the interrupt factors of the bus collision detection interrupt, uart2 transmission interrupt, and of uart2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection interrupt respectively. the start condition detection interrupt refers to the interrupt that occurs when the falling edge of the sda terminal (p7 0 ) is detected with the scl terminal (p7 1 ) staying h. the stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the sda terminal (p7 0 ) is detected with the scl terminal (p7 1 ) staying h. the bus busy flag (bit 2 of the uart2 special mode register) is set to 1 by the start condition detection, and set to 0 by the stop condition detection. in the first place, the control bits related to the iic bus(simplified iic bus) interface are explained. bit 0 of the uart special mode register (0377 16 ) is used as the iic mode selection bit. setting 1 in the iic mode select bit (bit 0) goes the circuit to achieve the iic bus interface effective. table 1.19.9 shows the relation between the iic mode select bit and respective control workings. since this function uses clock-synchronous serial i/o mode, set this bit to 0 in uart mode. p7 0 through p7 2 conforming to the simplified iic bus selector i/o timer delay noize filter timer uart2 selector (port p7 1 output data latch) i/o p7 0 /txd 2 /sda p7 1 /rxd 2 /scl reception register clk internal clock uart2 external clock selector uart2 i/o timer p7 2 /clk 2 arbitration start condition detection stop condition detection data bus falling edge detection d t q d t q d t q nack ack uart2 uart2 uart2 r uart2 transmission/ nack interrupt request uart2 reception/ack interrupt request dma1 request 9th pulse iicm=1 iicm=0 iicm=1 iicm=0 iicm=1 iicm=0 iicm=0 iicm=1 iicm=0 iicm=1 iicm=1 iicm=0 port reading * with iicm set to 1, the port terminal is to be readable even if 1 is assigned to p7 1 of the direction register. l-synchronous output enabling bit s r q bus busy iicm=1 iicm=0 bus collision/start, stop condition detection interrupt request bus collision detection noize filter transmission register to dma0, dma1 q noize filter to dma0 note 1: in m30623(80-pin package), p7 2 /clk 2 is not connected to external pin. figure 1.19.26. functional block diagram for iic mode
141 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development uart2 special mode register the acknowledgment non-detection interrupt refers to the interrupt that occurs when the sda terminal level is detected still staying h at the rising edge of the 9th transmission clock. the acknowledgment detection interrupt refers to the interrupt that occurs when sda terminals level is detected already went to l at the 9th transmission clock. also, assigning 1 1 0 1 (uart2 reception) to the dma1 request factor select bits provides the means to start up the dma transfer by the effect of acknowledgment detection. bit 1 of the uart2 special mode register (0377 16 ) is used as the arbitration loss detecting flag control bit. arbitration means the act of detecting the nonconformity between transmission data and sda terminal data at the timing of the scl rising edge. this detecting flag is located at bit 3 of the uart2 reception buffer register (037f 16 ), and 1 is set in this flag when nonconformity is detected. use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. when setting this bit to 1 and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to 1 at the falling edge of the 9th transmission clock. if update the flag byte by byte, must judge and clear (0) the arbitration lost detecting flag after complet- ing the first byte acknowledge detect and before starting the next one byte transmission. bit 3 of the uart2 special mode register is used as scl- and l-synchronous output enable bit. setting this bit to 1 goes the p7 1 data register to 0 in synchronization with the scl terminal level going to l.
142 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development uart2 special mode register 1. bus collision detect sampling clock select bit (bit 4 of the uart2 special mode register) 0: rising edges of the transfer clock clk timer a0 1: timer a0 overflow 2. auto clear function select bit of transmt enable bit (bit 5 of the uart2 special mode register) clk txd/rxd bus collision detect interrupt request bit transmit enable bit 3. transmit start condition select bit (bit 6 of the uart2 special mode register) clk txd enabling transmission clk txd rxd with "1: falling edge of rxd 2 " selected 0: in normal state txd/rxd note 1: in m30623(80-pin package), p7 2 /clk 2 is not connected to external pin. figure 1.19.27. some other functions added some other functions added are explained here. figure 1.19.27 shows their workings. bit 4 of the uart2 special mode register is used as the bus collision detect sampling clock select bit. the bus collision detect interrupt occurs when the rxd 2 level and txd 2 level do not match, but the nonconfor- mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to 0. if this bit is set to 1, the nonconformity is detected at the timing of the overflow of timer a0 rather than at the rising edge of the transfer clock. bit 5 of the uart2 special mode register is used as the auto clear function select bit of transmit enable bit. setting this bit to 1 automatically resets the transmit enable bit to 0 when 1 is set in the bus collision detect interrupt request bit (nonconformity). bit 6 of the uart2 special mode register is used as the transmit start condition select bit. setting this bit to 1 starts the txd transmission in synchronization with the falling edge of the rxd terminal.
143 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development uart2 special mode register s i/o3, 4 s i/o3 and s i/o4 are exclusive clock-synchronous serial i/os. in m30623(80-pin package), s in3 is not connected to external pin, so s i/o3 is exclusive transmission. figure 1.19.28 shows the s i/o3, 4 block diagram, and figure 1.19.29 shows the s i/o3, 4 control register. table 1.19.10 shows the specifications of s i/o3, 4. figure 1.19.28. s i/o3, 4 block diagram figure 1.19.29. s i/o3, 4 control register s i/o3, 4 s i/oi transmission/reception register (8) s i/o counter i (3) synchronous circuit f 1 f 8 f 32 data bus 8 s i/oi interrupt request smi5 lsb msb smi2 smi3 smi3 smi6 smi1 smi0 p9 0/ clk 3 (p9 5/ clk 4 ) p9 2/ s out3 (p9 6/ s out4 ) p9 1/ s in3 (p9 7/ s in4 ) transfer rate register (8) smi6 note 1: in m30623(80-pin package), p9 1 /s in3 is not connected to external pin. note 2: i = 3, 4. ni = a value set in the s i/o transfer rate register i (0363 16 , 0367 16 ). 1/(ni+1) 1/2 s i/oi control register (i = 3, 4) (note 1) symbol address when reset sic 0362 16 , 0366 16 40 16 b7 b6 b5 b4 b3 b2 b1 b0 w r description smi5 smi1 smi0 smi3 smi6 smi7 internal synchronous clock select bit transfer direction lect bit s i/oi port select bit (note 2) s out i initial value set bit 0 0 : selecting f 1 0 1 : selecting f 8 1 0 : selecting f 32 1 1 : not to be used b1 b0 0 : external clock 1 : internal clock effective when smi3 = 0 0 : l output 1 : h output 0 : input-output port 1 : s out i output, clk function bit name bit symbol synchronous clock select bit (note 2) 0 : lsb first 1 : msb first smi2 s out i high impedance control bit 0 : s out i output 1 : s out i high impedance note 1: set "1" in bit 2 of the protection register (000a 16 ) in advance to write to the s i/oi control register (i = 3, 4). note 2: when set ??to smi3 (i = 3, 4) and select input - output port, set ??to smi6 (i = 3, 4) and select internal clock, or input ??to p9 0 and p9 5 . nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be ??
144 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development uart2 special mode register table 1.19.10. specifications of s i/o3, 4 note 1: n is a value from 00 16 through ff 16 set in the s i/oi transfer rate register (i = 3, 4). note 2: with the external clock selected: ? to write to the s i/oi transmission/reception register (0360 16 , 0364 16 ), enter the h level to the clki terminal. also, to write to the bit 7 (s out i initial value set bit) of si/oi control register (0362 16 , 0366 16 ), enter the h level to the clki terminal. ? the s i/oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it, so stop the synchronous clock at the instant when it counts to eight. the internal clock, if selected, automatically stops. note 3: if the internal clock is used for the synchronous clock, the transfer clock signal stops at the h state. note 4: in m30623(80-pin package), s i/o3 is exclusive transmission, because s in3 is not connected to external pin. figure 1.19.30. si/oi related register item transfer data format transfer clock conditions for transmission/ reception start interrupt request generation timing select function specifications ? transfer data length: 8 bits ? with the internal clock selected (bit 6 of 0362 16 , 0366 16 = 1): f1/2(ni+1), f8/2(ni+1), f32/2(ni+1) (note 1) ? with the external clock selected (bit 6 of 0362 16 , 0366 16 = 0):input from the clki terminal (note 2) ? to start transmit/reception, the following requirements must be met: - select the synchronous clock (use bit 6 of 036216, 036616). select a frequency dividing ratio if the internal clock has been selected (use bits 0 and 1 of 0362 16 , 0366 16 ). - s out i initial value set bit (use bit 7 of 0362 16 , 0366 16 )= 1. - s i/oi port select bit (bit 3 of 0362 16 , 0366 16 ) = 1. - select the transfer direction (use bit 5 of 0362 16 , 0366 16 ) ? to use s i/oi interrupts, the following requirements must be met: - s i/oi interrupt request bit (bit 3 of 0049 16 , 0048 16 ) = 0. ? an interrupt occurs after counting eight transfer clock either in transmitting or receiving data. (note 3) - in transmitting: at the time data transfer from the s i/oi transmission/reception register finishes. - in receiving: at the time data reception to the s i/oi transmission/reception register finishes. ? lsb first or msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected. s i/o3, 4 si/oi bit rate generator b7 b0 symbol address when reset s3brg 0363 16 indeterminate s4brg 0367 16 indeterminate indeterminate assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r si/oi transmit/receive register b7 b0 symbol address when reset s3trr 0360 16 indeterminate s4trr 0364 16 indeterminate indeterminate transmission/reception starts by writing data to this register. after transmission/reception finishes, reception data is input. (note 1) w r note 1: in m30623(80-package), s i/o3 is exclusive transmission. b7
145 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development uart2 special mode register functions for setting an s out i initial value in carrying out transmission, the output level of the souti terminal as it is before transmitting 1-bit data can be set either to h or to l. figure 1.19.31 shows the timing chart for setting an souti initial value and how to set it. figure 1.19.31. timing chart for setting soutis initial value and how to set it s i/oi operation timing figure 1.19.32 shows the s i/oi operation timing figure 1.19.32. s i/oi operation timing chart s i/o3, 4 s i/oi port select bit smi3 = 0 souti initial value select bit smi7 = 1 (s out i: internal ??level) s i/oi port select bit smi3 = 0 1 (port select: normal port s out i) s out i terminal = ??output signal written to the s i/oi register =?? ?? ? (falling edge) s out i terminal = outputting stored data in the s i/oi transmission/ reception register signal written to the s i/oi transmission/reception register s out i (internal) s out i's initial value set bit (smi7) s out i terminal output s i/oi port select bit (smi3) setting the s out i initial value to h port selection (normal port s out i) d0 (i = 3, 4) initial value = ??(note) port output d0 (example) with ??selected for s out i: note: the set value is output only when the external clock has been selected. when initializing s out i, input ??level to clki pin. if the internal clock has been selected or if s out high impedance has been set, this output goes to the high-impedance state. d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 transfer clock (note 1) s i/oi output s out i s i/oi input s in i signal written to the s i/oi register (note 2) setting the s i/oi interrupt request bit note 1: with the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the s i/oi control register. (no frequency division, 8-division frequency, 32-division frequency.) note 2: with the internal clock selected for the transfer clock, the s out i terminal becomes to the high-impedance state after the transfer finishes. note 3: in m30623(80-pin package), the input pin s in3 of s i/o3 is not connected to external pin. (i= 3, 4) (note 3)
146 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development a-d converter item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock f ad (note 2) f ad /divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) (v cc = 5v) resolution 8-bit or 10-bit (selectable) absolute precision l 8-bit resolution 2lsb l 10-bit resolution 3lsb when the extended analog input pins anex0, anex1, an 00 to an 07, and an 20 to an 27 are used as the external operation amp connection mode: 7lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 8 pins (an 0 to an 7 ) + 2 pins (anex0 and anex1) + 16 pins (an 00 to an 07 , an 20 to an 27 ) (note 3) a-d conversion start condition ? software trigger a-d conversion starts when the a-d conversion start flag changes to 1 ? external trigger (can be retriggered) a-d conversion starts when the a-d conversion start flag is 1 and the ___________ ad trg /p9 7 input changes from h to l conversion speed per pin ? without sample and hold function 8-bit resolution: 49 f ad cycles , 10-bit resolution: 59 f ad cycles ? with sample and hold function 8-bit resolution: 28 f ad cycles , 10-bit resolution: 33 f ad cycles a-d converter the a-d converter consists of one 10-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p10 0 to p10 7 , p9 5 , p9 6 , p0 0 to p0 7 , and p2 0 to p2 7 also function as the analog signal input pins. the direction registers of these pins for a-d conversion must therefore be set to input. the vref connect bit (bit 5 at address 03d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage input pin (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after setting bit 5 of 03d7 16 to connect v ref . the result of a-d conversion is stored in the a-d registers of the selected pins. when set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. when set to 8-bit precision, the low 8 bits are stored in the even addresses. table 1.20.1 shows the performance of the a-d converter. figure 1.20.1 shows the block diagram of the a-d converter, and figures 1.20.2 and 1.20.3 show the a-d converter-related registers. note 1: does not depend on use of sample and hold function. note 2: divide the frequency if f(x in ) exceeds 10mh z , and make f ad frequency equal to 10mh z . without sample and hold function, set the f ad frequency to 250kh z min. with the sample and hold function, set the f ad frequency to 1mh z min. note 3: the pins are not used as the analog input pins can be used as normal i/o ports, or i/o pins of each peripheral function. table 1.20.1. performance of a-d converter
147 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development a-d converter figure 1.20.1. block diagram of a-d converter p2 0 /an 20 p2 1 /an 21 p2 2 /an 22 p2 3 /an 23 p2 4 /an 24 p2 5 /an 25 p2 6 /an 26 p2 7 /an 27 anex 0 anex 1 opa0 = 1 opa1 = 1 pm01,pm00 = 00 adgsel1,adgsel0 = 11 opa1,opa0 = 11 pm01,pm00 = 00 adgsel1,adgsel0 = 10 opa1,opa0 = 11 adgsel1,adgsel0 = 00 opa1,opa0 = 11 = 000 = 001 = 010 = 011 = 100 = 101 = 110 = 111 p10 0 /an 0 p10 1 /an 1 p10 2 /an 2 p10 3 /an 3 p10 4 /an 4 p10 5 /an 5 p10 6 /an 6 p10 7 /an 7 = 00000 = 00001 = 00010 = 00011 = 00100 = 00101 = 00110 = 00111 pm01,pm00,ch2,ch1,ch0 p0 0 /an 00 p0 1 /an 01 p0 2 /an 02 p0 3 /an 03 p0 4 /an 04 p0 5 /an 05 p0 6 /an 06 p0 7 /an 07 = 00000 = 00001 = 00010 = 00011 = 00100 = 00101 = 00110 = 00111 pm01,pm00,ch2,ch1,ch0 v ref v in ch2,ch1,ch0 pm00 pm01 decoder for channel selection a-d register 0 (16) a-d register 1 (16) a-d register 2 (16) a-d register 3 (16) a-d register 4 (16) a-d register 5 (16) a-d register 6 (16) a-d register 7 (16) (03c1 16 , 03c0 16 ) (03c3 16 , 03c2 16 ) (03c5 16 , 03c4 16 ) (03c7 16 , 03c6 16 ) (03c9 16 , 03c8 16 ) (03cb 16 , 03ca 16 ) (03cd 16 , 03cc 16 ) (03cf 16 , 03ce 16 ) a-d control register 0 (address 03d6 16 ) a-d control register 1 (address 03d7 16 ) successive conversion register resistor ladder data bus low-order v ref av ss vcut = 0 vcut = 1 f ad f ad 1/2 1/2 a-d conversion rate selection cks0 = 1 cks0 = 0 cks1 = 1 cks1 = 0 data bus high-order a-d control register 2 (address 03d4 16 ) decoder for a-d register opa1 = 1 port p10 group port p0 group port p2 group pm01,pm00 = 00 adgsel1,adgsel0 = 10 opa1,opa0 = 00 pm01,pm00 = 00 adgsel1,adgsel0 = 11 opa1,opa0 = 00 adgsel1,adgsel0 = 00 opa1,opa0 = 00 opa1,opa0 = 01 addresses comparator
148 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development a-d converter figure 1.20.2. a-d converter-related registers (1) a - d c o n t r o l r e g i s t e r 0 ( n o t e 1 ) s y m b o la d d r e s sw h e n r e s e t a d c o n 00 3 d 6 1 6 0 0 0 0 0 x x x 2 b 7b 6b 5b 4b 3b 2b 1b 0 a n a l o g i n p u t p i n s e l e c t b i t 0 0 0 : a n 0 i s s e l e c t e d 0 0 1 : a n 1 i s s e l e c t e d 0 1 0 : a n 2 i s s e l e c t e d 0 1 1 : a n 3 i s s e l e c t e d 1 0 0 : a n 4 i s s e l e c t e d 1 0 1 : a n 5 i s s e l e c t e d 1 1 0 : a n 6 i s s e l e c t e d( n o t e 2 ) 1 1 1 : a n 7 i s s e l e c t e d( n o t e 3 ) c h 0 b i t s y m b o lb i t n a m ef u n c t i o n c h 1 c h 2 a - d o p e r a t i o n m o d e s e l e c t b i t 0 0 0 : o n e - s h o t m o d e 0 1 : r e p e a t m o d e 1 0 : s i n g l e s w e e p m o d e 1 1 : r e p e a t s w e e p m o d e 0 r e p e a t s w e e p m o d e 1( n o t e 3 ) m d 0 m d 1 t r i g g e r s e l e c t b i t0 : s o f t w a r e t r i g g e r 1 : a d t r g t r i g g e r t r g a d s t a - d c o n v e r s i o n s t a r t f l a g0 : a - d c o n v e r s i o n d i s a b l e d 1 : a - d c o n v e r s i o n s t a r t e d f r e q u e n c y s e l e c t b i t 00 : f a d / 4 i s s e l e c t e d 1 : f a d / 2 i s s e l e c t e d c k s 0 w r a - d c o n t r o l r e g i s t e r 1 ( n o t e 1 ) s y m b o l a d d r e s sw h e n r e s e t a d c o n 10 3 d 7 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 a - d s w e e p p i n s e l e c t b i t s c a n 0 s c a n 1 m d 2 b i t s 8 / 1 0 - b i t m o d e s e l e c t b i t0 : 8 - b i t m o d e 1 : 1 0 - b i t m o d e v c u t o p a 0 v r e f c o n n e c t b i t o p a 1 a - d o p e r a t i o n m o d e s e l e c t b i t 1 0 : a n y m o d e o t h e r t h a n r e p e a t s w e e p m o d e 1 1 : r e p e a t s w e e p m o d e 1 0 : v r e f n o t c o n n e c t e d 1 : v r e f c o n n e c t e d e x t e r n a l o p - a m p c o n n e c t i o n m o d e b i t w r b 2 b 1 b 0 b 4 b 3 w h e n s i n g l e s w e e p a n d r e p e a t s w e e p m o d e 0 a r e s e l e c t e d 0 0 : a n 0 , a n 1 ( 2 p i n s ) 0 1 : a n 0 t o a n 3 ( 4 p i n s ) 1 0 : a n 0 t o a n 5 ( 6 p i n s ) 1 1 : a n 0 t o a n 7 ( 8 p i n s ) b 1 b 0 w h e n r e p e a t s w e e p m o d e 1 i s s e l e c t e d 0 0 : a n 0 ( 1 p i n ) 0 1 : a n 0 , a n 1 ( 2 p i n s ) 1 0 : a n 0 t o a n 2 ( 3 p i n s ) 1 1 : a n 0 t o a n 3 ( 4 p i n s )( n o t e 3 ) b 1 b 0 0 0 : a n e x 0 a n d a n e x 1 a r e n o t u s e d 0 1 : a n e x 0 i n p u t i s a - d c o n v e r t e d 1 0 : a n e x 1 i n p u t i s a - d c o n v e r t e d 1 1 : e x t e r n a l o p - a m p c o n n e c t i o n m o d e b 7 b 6 n o t e 1 : i f t h e a - d c o n t r o l r e g i s t e r i s r e w r i t t e n d u r i n g a - d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e . n o t e 2 : a n 0 0 t o a n 0 7 , a n d a n 2 0 t o a n 2 7 c a n b e u s e d t h e s a m e a s a n 0 t o a n 7 . n o t e 3 : w h e n c h a n g i n g a - d o p e r a t i o n m o d e , s e t a n a l o g i n p u t p i n a g a i n . f r e q u e n c y s e l e c t b i t 10 : f a d / 2 o r f a d / 4 i s s e l e c t e d 1 : f a d i s s e l e c t e d c k s 1 n o t e 1 : i f t h e a - d c o n t r o l r e g i s t e r i s r e w r i t t e n d u r i n g a - d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e . n o t e 2 : d i v i d e t h e f r e q u e n c y i f f ( x i n ) e x c e e d s 1 0 m h z , a n d m a k e f a d f r e q u e n c y e q u a l t o 1 0 m h z . n o t e 3 : a n 0 0 t o a n 0 7 , a n d a n 2 0 t o a n 2 7 c a n b e u s e d t h e s a m e a s a n 0 t o a n 7 . ( n o t e 2 )
149 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development a-d converter figure 1.20.3. a-d converter-related registers (2) a-d control register 2 (note) symbol address when reset adcon2 03d4 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function r w note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. a aa nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. a-d register i symbol address when reset adi(i=0 to 7) 03c0 16 to 03cf 16 indeterminate eight low-order bits of a-d conversion result function r w (b15) b7 b7 b0 b0 (b8) during 10-bit mode two high-order bits of a-d conversion result nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. during 8-bit mode when read, the content is indeterminate a a smp a a 0 adgsel0 adgsel1 analog input group select bit 00 : port10 group is selected 01 : not use 10 : port0 group is selected 11 : port1 group is selected b2 b1 reserved bit always set to 0 a a
150 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development a-d converter (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conver- sion. table 1.20.2 shows the specifications of one-shot mode. figure 1.20.4 shows the a-d control regis- ter in one-shot mode. table 1.20.2. one-shot mode specifications figure 1.20.4. a-d conversion register in one-shot mode a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit w r 00 invalid in one-shot mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected (note 2) 1 1 1 : an 7 is selected (note 3) b2 b1 b0 0 0 : one-shot mode (note 3) b4 b3 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: an 00 to an 07 , and an 20 to an 27 can be used the same as an 0 to an 7 . note 3: when changing a-d operation mode, set analog input pin again. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 0 : any mode other than repeat sweep mode 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: divide the frequency if f(x in ) exceeds 10mhz, and make f ad frequency equal to 10mhz. a a aa aa a a aa aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa (note 2) item specification function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-d conversion start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin one of an 0 to an 7 , as selected (note 1) reading of result of a-d converter read a-d register corresponding to selected pin note 1: an 00 to an 07 , and an 20 to an 27 can be used the same as an 0 to an 7 .
151 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development a-d converter (2) repeat mode i n repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conversion. table 1.20.3 shows the specifications of repeat mode. figure 1.20.5 shows the a-d control register in repeat mode. a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit w r 01 invalid in repeat mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected (note 2) 1 1 1 : an 7 is selected (note 3) b2 b1 b0 0 1 : repeat mode (note 3) b4 b3 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: an 00 to an 07 , and an 20 to an 27 can be used the same as an 0 to an 7 . note 3: when changing a-d operation mode, set analog input pin again. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 0 : any mode other than repeat sweep mode 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: divide the frequency if f(x in ) exceeds 10mhz, and make f ad frequency equal to 10mhz. aa a aa a aa a aa a aa aa a a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a (note 2) figure 1.20.5. a-d conversion register in repeat mode item specification function the pin selected by the analog input pin select bit is used for repeated a-d conversion star condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of an 0 to an 7 , as selected (note 1) reading of result of a-d converter read a-d register corresponding to selected pin table 1.20.3. repeat mode specifications note 1: an 00 to an 07 , and an 20 to an 27 can be used the same as an 0 to an 7 .
152 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development a-d converter (3) single sweep mode i n single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a-d conversion. table 1.20.4 shows the specifications of single sweep mode. figure 1.20.6 shows the a-d control register in single sweep mode. table 1.20.4. single sweep mode specifications figure 1.20.6. a-d conversion register in single sweep mode a - d c o n t r o l r e g i s t e r 0 ( n o t e 1 ) s y m b o la d d r e s sw h e n r e s e t a d c o n 00 3 d 6 1 6 0 0 0 0 0 x x x 2 b 7b 6b 5b 4b 3b 2b 1b 0 a n a l o g i n p u t p i n s e l e c t b i t c h 0 b i t s y m b o lb i t n a m ef u n c t i o n c h 1 c h 2 a - d o p e r a t i o n m o d e s e l e c t b i t 0 1 0 : s i n g l e s w e e p m o d e m d 0 m d 1 t r i g g e r s e l e c t b i t0 : s o f t w a r e t r i g g e r 1 : a d t r g t r i g g e r t r g a d s t a - d c o n v e r s i o n s t a r t f l a g0 : a - d c o n v e r s i o n d i s a b l e d 1 : a - d c o n v e r s i o n s t a r t e d f r e q u e n c y s e l e c t b i t 00 : f a d / 4 i s s e l e c t e d 1 : f a d / 2 i s s e l e c t e d c k s 0 w r a - d c o n t r o l r e g i s t e r 1 ( n o t e 1 ) s y m b o la d d r e s sw h e n r e s e t a d c o n 10 3 d 7 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 a - d s w e e p p i n s e l e c t b i t s c a n 0 s c a n 1 m d 2 b i t s 8 / 1 0 - b i t m o d e s e l e c t b i t0 : 8 - b i t m o d e 1 : 1 0 - b i t m o d e v c u t o p a 0 v r e f c o n n e c t b i t 0 : a n y m o d e o t h e r t h a n r e p e a t s w e e p m o d e 1 o p a 1 a - d o p e r a t i o n m o d e s e l e c t b i t 1 1 : v r e f c o n n e c t e d e x t e r n a l o p - a m p c o n n e c t i o n m o d e b i t ( n o t e 4 ) w r 1 0 i n v a l i d i n s i n g l e s w e e p m o d e 0 b 4 b 3 w h e n s i n g l e s w e e p a n d r e p e a t s w e e p m o d e 0 a r e s e l e c t e d 0 0 : a n 0 , a n 1 ( 2 p i n s ) 0 1 : a n 0 t o a n 3 ( 4 p i n s ) 1 0 : a n 0 t o a n 5 ( 6 p i n s ) 1 1 : a n 0 t o a n 7 ( 8 p i n s ) b 1 b 0 0 0 : a n e x 0 a n d a n e x 1 a r e n o t u s e d 0 1 : a n e x 0 i n p u t i s a - d c o n v e r t e d 1 0 : a n e x 1 i n p u t i s a - d c o n v e r t e d 1 1 : e x t e r n a l o p - a m p c o n n e c t i o n m o d e b 7 b 6 1 n o t e 1 : i f t h e a - d c o n t r o l r e g i s t e r i s r e w r i t t e n d u r i n g a - d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e . f r e q u e n c y s e l e c t b i t 1 0 : f a d / 2 o r f a d / 4 i s s e l e c t e d 1 : f a d i s s e l e c t e d c k s 1 ( n o t e 3 ) ( n o t e 2 ) n o t e 1 : i f t h e a - d c o n t r o l r e g i s t e r i s r e w r i t t e n d u r i n g a - d c o n v e r s i o n , t h e c o n v e r s i o n r e s u l t i s i n d e t e r m i n a t e . n o t e 2 : d i v i d e t h e f r e q u e n c y i f f ( x i n ) e x c e e d s 1 0 m h z , a n d m a k e f a d f r e q u e n c y e q u a l t 1 0 m h item specification function the pins selected by the a-d sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d converter start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) (note 1) reading of result of a-d converter read a-d register corresponding to selected pin note 1: an 00 to an 07 , and an 20 to an 27 can be used the same as an 0 to an 7 .
153 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development a-d converter (4) repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. table 1.20.5 shows the specifications of repeat sweep mode 0. figure 1.20.7 shows the a-d control register in repeat sweep mode 0. figure 1.20.7. a-d conversion register in repeat sweep mode 0 a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit 0 : any mode other than repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 4) w r 1 1 invalid in repeat sweep mode 0 0 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: divide the frequency if f(x in ) exceeds 10mhz, and make f ad frequency equal to 10mhz. note 3: an 00 to an 07 , and an 20 to an 27 can be used the same as an 0 to an 7 . note 4: neither ?1?nor ?0?can be selected with the external op-amp connection mode bit. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a (note 2) (note 3) item specification function the pins selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) (note 1) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) table 1.20.5. repeat sweep mode 0 specifications note 1: an 00 to an 07 , and an 20 to an 27 can be used the same as an 0 to an 7 .
154 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development a-d converter item specification function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit example : an 0 selected an 0 an 1 an 0 an 2 an 0 an 3 , etc start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 (1 pin), an 0 and an 1 (2 pins), an 0 to an 2 (3 pins), an 0 to an 3 (4 pins) (note1 ) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) (5) repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins selected using the a-d sweep pin select bit. table 1.20.6 shows the specifications of repeat sweep mode 1. figure 1.20.8 shows the a-d control register in repeat sweep mode 1. a-d control register 0 (note 1) symbol address when reset adcon0 03d6 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit 1 : repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 4) w r 1 1 invalid in repeat sweep mode 1 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: divide the frequency if f(x in ) exceeds 10mhz, and make f ad frequency equal to 10mhz. note 3: an 00 to an 07 , and an 20 to an 27 can be used the same as an 0 to an 7 . note 4: neither ?1?nor ?0?can be selected with the external op-amp connection mode bit. b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 0 0 : anex0 and anex1 are not used 0 1 : anex0 input is a-d converted 1 0 : anex1 input is a-d converted 1 1 : external op-amp connection mode b7 b6 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 a aa a a aa aa a aa a aa a aa a aa a aa a aa a aa a a aa aa a a aa aa a a aa aa a a aa aa a aa a aa a aa (note 2) (note 3) figure 1.20.8. a-d conversion register in repeat sweep mode 1 table 1.20.6. repeat sweep mode 1 specifications note 1: an 00 to an 07 , and an 20 to an 27 can be used the same as an 0 to an 7 .
155 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development a-d converter (a) sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 03d4 16 ) to 1. when sample and hold is selected, the rate of conversion of each pin increases. as a result, a 28 f ad cycle is achieved with 8-bit resolution and 33 f ad with 10-bit resolution. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used. (b) extended analog input pins in one-shot mode and repeat mode, the input via the extended analog input pins anex0 and anex1 can also be converted from analog to digital. when bit 6 of the a-d control register 1 (address 03d7 16 ) is 1 and bit 7 is 0, input via anex0 is converted from analog to digital. the result of conversion is stored in a-d register 0. when bit 6 of the a-d control register 1 (address 03d7 16 ) is 0 and bit 7 is 1, input via anex1 is converted from analog to digital. the result of conversion is stored in a-d register 1. furthermore, the input via 16pins of the extended analog input pins an 00 to an 07 , an 20 to an 27 can be converted from analog to digital. these pins can be used the same as an 0 to an 7 . use the a-d control register 2 (address 03d4 16 ) bit 1 and bit 2 to select the pin group an 0 to an 7 , an 00 to an 07 , an 20 to an 27 . in the selected pin group, the pins is not used as the analog input pin, can be used as normal i/o ports, or i/o pins of each peripheral function. (c) external operation amp connection mode in this mode, multiple external analog inputs via the extended analog input pins, anex0 and anex1, can be amplified together by just one operation amp and used as the input for a-d conversion. when bit 6 of the a-d control register 1 (address 03d7 16 ) is 1 and bit 7 is 1, input via an 0 to an 7 (note 1) is output from anex0. the input from anex1 is converted from analog to digital and the result stored in the corresponding a-d register. the speed of a-d conversion depends on the response of the external operation amp. do not connect the anex0 and anex1 pins directly. figure 1.20.9 is an example of how to connect the pins in external operation amp mode. note 1: an 00 to an 07 , an 20 to an 27 can be used the same as an 0 to an 7 . (d) caution of using a-d converter (1) set the direction register of the following ports to input: the port corresponding to a pin to be used as an analog input pin and external trigger input pin(p9 7 ). (2) in using a key-input interrupt, none of 4 pins (an 4 through an 7) can be used as an a-d conversion port (if the a-d input voltage goes to l level, a key-input interrupt occurs). (3) insert the capacitor between avcc and avss, between v ref and avss, and between the analog input pin (an i ) and avss, to prevent a malfunction or program runaway, and to reduce conversion error, due to noise. figure 1.20.10 is an example connection of each pin.
156 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development a-d converter an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 00 an 01 an 02 an 03 an 04 an 05 an 06 an 07 adgsel1,adgsel0 = 0,0 adgsel1,adgsel0 = 1,0 an 20 an 21 an 22 an 23 an 24 an 25 an 26 an 27 adgsel1,adgsel0 = 1,1 anex 0 anex 1 analog input pins resistor ladder successive conversion register external op-amp comparator port p10 group analog input pins port p0 group analog input pins port p2 group v c c a v c c v s s a v s s a n i c 4 c 1 c 3 c 2 v r e f m i c r o c o m p u t e r n o t e 1 : c 1 3 0 . 4 7 m f , c 2 3 0 . 4 7 m f , c 3 3 1 0 0 p f , c 4 3 0 . 1 m f n o t e 2 : u s e t h i c k a n d s h o r t e s t p o s s i b l e w i r i n g t o c o n n e c t c a p a c i t o r s . figure 1.20.9. example of external op-amp connection mode figure 1.20.10. example connection of v cc , v ss , av cc , av ss , v ref and an i
157 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development d-a converter d-a converter this is an 8-bit, r-2r type d-a converter. the microcomputer contains two independent d-a converters of this type. d-a conversion is performed when a value is written to the corresponding d-a register. bits 0 and 1 (d-a output enable bits) of the d-a control register decide if the result of conversion is to be output. do not set the target port to output mode if d-a conversion is to be performed. output analog voltage (v) is determined by a set value (n : decimal) in the d-a register. v = v ref x n/ 256 (n = 0 to 255) v ref : reference voltage table 1.21.1 lists the performance of the d-a converter. figure 1.21.1 shows the block diagram of the d-a converter. figure 1.21.2 shows the d-a control register. figure 1.21.3 shows the d-a converter equivalent circuit. item performance conversion method r-2r method resolution 8 bits analog output pin 2 channels table 1.21.1. performance of d-a converter aaa p9 3 /da 0 aaa p9 4 /da 1 data bus low-order bits d-a register0 (8) r-2r resistor ladder d-a0 output enable bit d-a register1 (8) r-2r resistor ladder d-a1 output enable bit (address 03d8 16 ) (address 03da 16 ) figure 1.21.1. block diagram of d-a converter
158 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development d-a converter figure 1.21.2. d-a control register d-a control register symbol address when reset dacon 03dc 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a0 output enable bit da0e bit symbol bit name function r w 0 : output disabled 1 : output enabled d-a1 output enable bit 0 : output disabled 1 : output enabled da1e nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ? d-a register symbol address when reset dai (i = 0,1) 03d8 16 , 03da 16 indeterminate w r b7 b0 function r w output value of d-a conversion aa a aa a aa aa a a v ref av ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r da0 msb lsb d-a0 output enable bit "0" "1" d-a0 register0 note 1: the above diagram shows an instance in which the d-a register is assigned 2a 16 . note 2: the same circuit as this is also used for d-a1. note 3: to reduce the current consumption when the d-a converter is not used, set the d-a output enable bit to 0 and set the d-a register to 00 16 so that no current flows in the resistors rs and 2rs. figure 1.21.3. d-a converter equivalent circuit
159 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development crc crc calculation circuit the cyclic redundancy check (crc) calculation circuit detects an error in data blocks. the microcom- puter uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) to generate crc code. the crc code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. the crc code is set in a crc data register each time one byte of data is transferred to a crc input register after writing an initial value into the crc data register. generation of crc code for one byte of data is com- pleted in two machine cycles. figure 1.22.1 shows the block diagram of the crc circuit. figure 1.22.2 shows the crc-related registers. figure 1.22.3 shows the calculation example using the crc calculation circuit figure 1.22.2. crc-related registers symbol address when reset crcd 03bd 16 , 03bc 16 indeterminate b7 b0 b7 b0 (b15) (b8) crc data register w r crc calculation result output register function values that can be set 0000 16 to ffff 16 symbo address when reset crcin 03be 16 indeterminate b7 b0 crc input register w r data input register function values that can be set 00 16 to ff 16 a a a a aaaaaa eight low-order bits aaaaaa eight high-order bits data bus high-order bits data bus low-order bits aaaaaaaaaa aaaaaaaaaa aaaaaa aaaaaa crc data register (16) crc input register (8) aaaaaaaaaa aaaaaaaaaa crc code generating circuit x 16 + x 12 + x 5 + 1 (addresses 03bd 16 , 03bc 16 ) (address 03be 16 ) figure 1.22.1. block diagram of crc circuit
160 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development crc b15 b0 (1) setting 0000 16 crc data register crcd [03bd 16 , 03bc 16 ] b0 b7 b15 b0 (2) setting 01 16 crc input register crcin [03be 16 ] 2 cycles after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 1189 16 stores crc code b0 b7 b15 b0 (3) setting 23 16 crc input register crcin [03be 16 ] after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 0a41 16 stores crc code the code resulting from sending 01 16 in lsb first mode is (1000 0000). thus the crc code in the generating polynomial, (x 16 + x 12 + x 5 + 1), becomes the remainder resulting from dividing (1000 0000) x 16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. thus the crc code becomes (1001 0001 1000 1000). since the operation is in lsb first mode, the (1001 0001 1000 1000) corresponds to 1189 16 in hexadecimal notation. if the crc operation in msb first mode is necessary in the crc operation circuit built in the m16c, switch between the lsb side and the msb side of the input-holding bits, and carry out the crc operation. also switch between the msb and lsb of the result as stored in crc data. 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb msb lsb msb 98 1 1 modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 figure 1.22.3. calculation example using the crc calculation circuit
161 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development programmable i/o port programmable i/o ports m30622(100-pin package) has 87 programmable i/o ports: p0 to p10 (excluding p8 5 ). m30623(80-pin package) has 70 (p1, p4 4 to p4 7 , p7 2 to p7 5 , p9 1 are not connected to external pin). each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. p8 5 is an input-only port and has no built-in pull-up resistance. figures 1.23.1 to 1.23.3 show the programmable i/o ports. figure 1.23.4 shows the i/o pins. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices (other than the d-a con- verter), they function as outputs regardless of the contents of the direction registers. when pins are to be used as the outputs for the d-a converter, do not set the direction registers to output mode. see the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) direction registers figure 1.23.5 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these regis- ters corresponds one for one to each i/o pin. note: there is no direction register bit for p8 5 . (2) port registers figure 1.23.6 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. (3) pull-up control registers figure 1.23.7 shows the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. however, in memory expansion mode and microprocessor mode, p0 to p5 operate as the bus and the pull-up control register setting is invalid. (4) port control register figure 1.23.8 shows the port control register. the bit 0 of port control resister is used to read port p1 as follows: 0 : when port p1 is input port, port input level is read. when port p1 is output port , the contents of port p1 register is read. 1 : the contents of port p1 register is read always. this register is valid in the following: ? external bus width is 8 bits in microprocessor mode or memory expansion mode. ? port p1 can be used as a port in multiplexed bus for the entire space.
162 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development programmable i/o port figure 1.23.1. programmable i/o ports (1) p0 0 to p0 7 , p2 0 to p2 7 p1 0 to p1 4 (inside dotted-line not included) p1 5 to p1 7 (inside dotted-line included) note 1: symbolizes a parasitic diode. do not apply a voltage higher than vcc to each port. note 2: in m30623(80-pin package), p1 0 to p1 7 , p4 4 to p4 7 , p7 2 to p7 5 , and p9 1 are not connected to external pin. direction register port latch pull-up selection data bus input to respective peripheral functions "1" output (note 1) data bus direction register pull-up selection port latch (note 1) pull-up selection data bus direction register pull-up selection port latch (note 1) input to respective peripheral functions p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 4 , p5 6 p5 7 , p6 0 , p6 1 , p6 4 , p6 5 , p7 2 to p7 6 , p8 0 , p8 1 , p9 0 , p9 2 p5 5 , p6 2 , p6 6 , p7 7 , p9 1 , p9 7 p6 3 , p6 7 (inside dotted-line not included) direction register port latch port p1 control register data bus input to respective peripheral functions (note 1) analog input inside dotted-line included inside dotted-line not included inside dotted-line included
163 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development programmable i/o port figure 1.23.2. programmable i/o ports (2) p8 2 to p8 4 data bus direction register pull-up selection port latch input to respective peripheral functions (note 1) p7 0 , p7 1 p8 6 p8 7 "1" output direction register pull-up selection port latch data bus (note 1) data bus direction register pull-up selection port latch (note 1) rf fc rd "1" output direction register port latch input to respective peripheral functions (note 2) data bus note 1: symbolizes a parasitic diode. do not apply a voltage higher than vcc to each port. note 2: symbolizes a parasitic diode. note 3: in m30623(80-pin package), p1 0 to p1 7 , p4 4 to p4 7 , p7 2 to p7 5 , and p9 1 are not connected to external pin.
164 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development programmable i/o port figure 1.23.3. programmable i/o ports (3) p9 3 , p9 4 p10 0 to p10 3 (inside dotted-line not included) p10 4 to p10 7 (inside dotted-line included) data bus direction register pull-up selection port latch analog input input to respective peripheral functions (note 1) d-a output enabled direction register pull-up selection port latch data bus input to respective peripheral functions d-a output enabled analog output (note 1) p9 5 (inside dotted-line included) p8 5 data bus nmi interrupt input (note 1) p9 6 (inside dotted-line not included) "1" output direction register pull-up selection port latch data bus analog input input to respective peripheral functions (note 1) note 1: symbolizes a parasitic diode. do not apply a voltage higher than vcc to each port. note 2: in m30623(80-pin package), p1 0 to p1 7 , p4 4 to p4 7 , p7 2 to p7 5 , and p9 1 are not connected to external pin.
165 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development programmable i/o port figure 1.23.4. i/o pins note 1: symbolizes a parasitic diode. do not apply a voltage higher than vcc to each pin. byte byte signal input (note 1) cnv ss cnv ss signal input (note 1) reset reset signal input (note 1) mask rom version(inside dotted-line not included) onetime prom version(inside dotted-line included) to circuit of prom-programming
166 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development programmable i/o port figure 1.23.5. direction register port pi direction register (note 1) symbol address when reset pdi (i = 0 to 10, except 8) 03e2 16 , 03e3 16 , 03e6 16 , 03e7 16 , 03ea 16 00 16 03eb 16 , 03ee 16 , 03ef 16 , 03f3 16 , 03f6 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 direction register pdi_1 port pi 1 direction register pdi_2 port pi 2 direction register pdi_3 port pi 3 direction register pdi_4 port pi 4 direction register pdi_5 port pi 5 direction register pdi_6 port pi 6 direction register pdi_7 port pi 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (i = 0 to 10 except 8) port p8 direction register symbol address when reset pd8 03f2 16 00x00000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd8_0 port p8 0 direction register pd8_1 port p8 1 direction register pd8_2 port p8 2 direction register pd8_3 port p8 3 direction register pd8_4 port p8 4 direction register nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate. pd8_6 port p8 6 direction register pd8_7 port p8 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) note 1: set bit 2 of protect register (address 000a 16 ) to ??before rewriting to the port p9 direction register. note 2: in m30623(80-pin package), p1, p4 4 to p4 7 , p7 2 to p7 5 , and p9 1 are not connected to external pin, but exist inside microcomputer. so set these ports for output mode. a aa a a aa aa a aa a a aa aa a aa a aa a a aa aa a aa a aa a aa a a aa aa a aa a a aa aa a aa a aa
167 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development programmable i/o port figure 1.23.6. port register port pi register symbol address when reset pi (i = 0 to 10, except 8) 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 , 03e8 16 indeterminate 03e9 16 , 03ec 16 , 03ed 16 , 03f1 16 , 03f4 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 register pi_1 port pi 1 register pi_2 port pi 2 register pi_3 port pi 3 register pi_4 port pi 4 register pi_5 port pi 5 register pi_6 port pi 6 register pi_7 port pi 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data (note) (i = 0 to 10 except 8) port p8 register symbol address when reset p8 03f0 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 p8_0 port p8 0 register p8_1 port p8 1 register p8_2 port p8 2 register p8_3 port p8 3 register p8_4 port p8 4 register p8_5 port p8 5 register p8_6 port p8 6 register p8_7 port p8 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for p8 5 ) 0 : ??level data 1 : ??level data a aa a aa a aa a a aa aa a aa a aa a aa a aa a aa a aa a aa a a aa aa a aa a aa a aa a aa a a aa aa a a note 1: since p7 0 and p7 1 are n-channel open drain ports, the data is high-impedance. note 2: in m30623(80-pin package), p1, p4 4 to p4 7 , p7 2 to p7 5 , and p9 1 are not connected to external pin, but exist inside microcomputer. so set these ports for output mode.
168 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development programmable i/o port figure 1.23.7. pull-up control register pull-up control register 0 symbol address when reset pur0 03fc 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu02 p1 0 to p1 3 pull-up pu03 p1 4 to p1 7 pull-up pu04 p2 0 to p2 3 pull-up pu05 p2 4 to p2 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high aa a aa aa a a aa a aa aa a a aa a aa a aa a aa a pull-up control register 1 symbol address when reset pur1 03fd 16 00 16 (note 2) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu10 p4 0 to p4 3 pull-up pu11 p4 4 to p4 7 pull-up pu12 p5 0 to p5 3 pull-up pu13 p5 4 to p5 7 pull-up pu14 p6 0 to p6 3 pull-up pu15 p6 4 to p6 7 pull-up pu16 p7 0 to p7 3 pull-up (note 1) pu17 p7 4 to p7 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high note 1: since p7 0 and p7 1 are n-channel open drain ports, pull-up is not available for them. note 2: when the v cc level is being impressed to the cnv ss terminal, this register becomes to 02 16 when reset (pu11 becomes to 1). note 3: in m30623(80-pin package), p4 4 to p4 7 , and p7 2 to p7 5 are not connected to external pin, but exist inside microcomputer. so set these ports for output mode. aa aa a a aa a aa aa a a aa a aa a aa a aa a aa a pull-up control register 2 symbol address when reset pur2 03fe 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu20 p8 0 to p8 3 pull-up pu21 p8 4 to p8 7 pull-up (except p8 5 ) pu22 p9 0 to p9 3 pull-up pu23 p9 4 to p9 7 pull-up pu24 p10 0 to p10 3 pull-up pu25 p10 4 to p10 7 pull-up nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be 0. the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high aa a aa a aa a aa aa a a aa a aa aa a a note 1: in m30623(80-pin package), p1 is not connected to external pin, but exist inside microcomputer. so set this port for output mode. note 1: in m30623(80-pin package), p1 is not connected to external pin, but exist inside microcomputer. so set this port for output mode.
169 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development programmable i/o port figure 1.23.8. port control register port control register symbpl address when reset pcr 03ff 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pcr0 port p1 control register 0 : when input port, read port input level. when output port, read the contents of port p1 register. 1 : read the contents of port p1 register though input/output port. nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? aa a
170 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development programmable i/o port pin name connection ports p0 to p10 (excluding p8 5 ) (note 1) x out (note 2) av ss , v ref , byte av cc after setting for input mode, connect every pin to v ss or v cc via a resistor; or after setting for output mode, leave these pins open. open connect to v cc connect to v ss note 1: in m30623(80-pin package), p1, p4 4 to p4 7 , p7 2 to p7 5 , and p9 1 are not connected to external pin, but exist inside microcomputer. so set these ports for output mode. note 2: with external clock input to x in pin. nmi connect via resistor to v cc (pull-up) table 1.23.1. example connection of unused pins in single-chip mode pin name connection ports p6 to p10 (excluding p8 5 ) (note 1) av ss , v ref av cc after setting for input mode, connect every pin to v ss or v cc via a resistor; or after setting for output mode, leave these pins open. open connect to v cc connect to v ss note 1: in m30623(80-pin package), p7 2 to p7 5 , p9 1 are not connected to external pin, but exist inside microcomputer. so set these ports for output mode. note 2: with external clock input to x in pin. note 3: the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. hold, rdy, nmi connect via resistor to v cc (pull-up) bhe, ale, hlda, x out (note 2), bclk p4 5 / cs1 to p4 7 / cs3 sets ports to input mode, sets bits cs1 through cs3 to 0, and connects to vcc via resistors (pull-up). figure 1.23.9. example connection of unused pins port p0 to p10 (except for p8 5 ) (input mode) (input mode) (output mode) nmi x out av cc byte av ss v ref microcomputer v cc v ss in single-chip mode port p6 to p10 (except for p8 5 ) (input mode) (input mode) (output mode) nmi x out av cc av ss v ref open microcomputer v cc v ss in memory expansion mode or in microprocessor mode hold rdy ale bclk bhe hlda open open open port p4 5 / cs1 to p4 7 / cs3 note 1: in m30623(80-pin package), p7 2 to p7 5 , p9 1 are not connected to external pin, but exist inside microcomputer. so set these ports for output mode. note 2: the m16c/62t group is not guaranteed to operate in memory expansion and microprocessor modes. note 3: when the wiring between nmi and v cc is long, pull-up via resistor. table 1.23.2. example connection of unused pins in memory expansion mode and microprocessor mode
171 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development usage precaution timer a (timer mode) usage precaution timer a (event counter mode) (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff 16 by underflow or 0000 16 by overflow. reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. (2) when stop counting in free run type, set timer again. (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff 16 . reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. (1) setting the count start flag to 0 while a count is in progress causes as follows: ? the counter stops counting and a content of reload register is reloaded. ? the tai out pin outputs l level. ? the interrupt request generated and the timer ai interrupt request bit goes to 1. (2) the timer ai interrupt request bit goes to 1 if the timer's operation mode is set using any of the following procedures: ? selecting one-shot timer mode after reset. ? changing operation mode from timer mode to one-shot timer mode. ? changing operation mode from event counter mode to one-shot timer mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. timer a (one-shot timer mode) (1) the timer ai interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures: ? selecting pwm mode after reset. ? changing operation mode from timer mode to pwm mode. ? changing operation mode from event counter mode to pwm mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. (2) setting the count start flag to 0 while pwm pulses are being output causes the counter to stop counting. if the tai out pin is outputting an h level in this instance, the output level goes to l, and the timer ai interrupt request bit goes to 1. if the tai out pin is outputting an l level in this instance, the level does not change, and the timer ai interrupt request bit does not becomes 1. timer a (pulse width modulation mode) timer b (timer mode, event counter mode) (1) reading the timer bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. reading the timer bi register with the reload timing gets ffff 16 . reading the timer bi register after setting a value in the timer bi register with a count halted but before the counter starts counting gets a proper value.
172 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development usage precaution stop mode and wait mode a-d converter (1) if changing the measurement mode select bit is set after a count is started, the timer bi interrupt request bit goes to 1. (2) when the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. timer b (pulse period/pulse width measurement mode) interrupts (1) write to each bit (except bit 6) of a-d control register 0, to each bit of a-d control register 1, and to bit 0 of a-d control register 2 when a-d conversion is stopped (before a trigger occurs). in particular, when the vref connection bit is changed from 0 to 1, start a-d conversion after an elapse of 1 m s or longer. (2) when changing a-d operation mode, select analog input pin again. (3) using one-shot mode or single sweep mode read the correspondence a-d register after confirming a-d conversion is finished. (it is known by a- d conversion interrupt request bit.) (4) using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 use the undivided main clock as the internal cpu clock. (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. _______ when using the nmi interrupt, initialize the stack point at the beginning of a program. concerning _______ the first instruction immediately after reset, generating any interrupts including the nmi interrupt is prohibited. _______ (3) the nmi interrupt _______ ? as for the nmi interrupt pin, an interrupt cannot be disabled. connect it to the v cc pin via a resistor (pull-up) if unused. be sure to work on it. _______ ? do not get either into stop mode with the nmi pin set to l. ____________ (1) when returning from stop mode by hardware reset, reset pin must be set to l level until main clock oscillation is stabilized. (2) when switching to either wait mode or stop mode, instructions occupying four bytes either from the wait instruction or from the instruction that sets the every-clock stop bit to 1 within the instruction queue are prefetched and then the program stops. so put at least four nops in succession either to the wait instruction or to the instruction that sets the every-clock stop bit to 1.
173 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development usage precaution (4) external interrupt _______ _______ ? when the polarity of the int0 to int5 pins is changed, the interrupt request bit is sometimes set to "1". after changing the polarity, set the interrupt request bit to "0". example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; four nop instructions are required when using hold function. nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; push flag register onto stack fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions (four when using the hold function) or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) rewrite the interrupt control register ? to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: ? when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. this will depend on the instruction. if this creates problems, use the below in- structions to change the register. instructions : and, or, bclr, bset note 1: _______ _______ in m30623 (80-pin package), can not use int 3 to int 5 as the interrupt factors, because _______ _______ p1 5 /d 13 /int 3 to p1 7 /d 15 /int 5 have no corresponding external pin.
174 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development usage precaution usage precaution of built-in prom version (1) all built-in prom versions high voltage is required to program to the built-in prom. be careful not to apply excessive voltage. be especially careful during power-on. (2) one time prom version one time prom versions shipped in blank (m30622ectfp/ecvfp, m30623ectgp/ecvgp), of which built-in proms are programmed by users, are also provided. for these microcomputers, a programming test and screening are not performed in the assembly process and the following pro- cesses. to improve their reliability after programming, we recommend to program and test as flow shown in figure 1.24.1 before use. but, in case of using as the test of cars loading, mass production, correspond to programming prom, and screened shipped in programming, please require. programming with prom programmer screening (note 1) (leave at 150?c for 40 hours) verify test prom programmer rom data check in all numbers, target device (high temperature, low temperature) (note 2) vcc=5.5v, 5.0v, 4.5v note 1: never expose to 150?c exceeding 100 hours. note 2: test in responce to using temperature limit. figure 1.24.1. programming and test flow for one time prom version
175 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development items to be submitted when ordering masked rom version please submit the following when ordering masked rom products: (1) mask rom confirmation form (2) mark specification sheet (3) rom data : eproms or floppy disks *: in the case of eproms, there sets of eproms are required per pattern. *: in the case of floppy disks, 3.5-inch double-sided high-density disk (ibm format) is required per pattern. items to be submitted when ordering data to be written to rom please submit the following when ordering data to be written to one-time prom products at the factory: (1) rom writing order form (2) mark specification sheet (3) rom data : eproms or floppy disks *: in the case of eproms, there sets of eproms are required per pattern. *: in the case of floppy disks, 3.5-inch double-sided high-density disk (ibm format) is required per pattern.
176 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development electrical characteristics table 1.26.1. absolute maximum ratings note 1: when writing to eprom ,only cnvss is C0.3 to 13.5 (v) . note 2: in case of 85 c guaranteed version, - 40 c to 85 c. in case of 125 c guaranteed version, - 40 c to 125 c. note 3: in m30623(80-pin package), p1 0 to p1 7 , p4 4 to p4 7 ,p7 2 to p7 5 ,and p9 1 are not connected to the external pin. 4.2 (note 1) 5.5 vcc 5.0 vcc avcc v v 0 0 v ih i oh (avg) ma ma vss avss 0.8vcc v v v v vcc 0.2vcc 0.2vcc 0 0 i oh (peak) p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7 , -5 -10 p0 0 to p0 7 , p1 0 to p1 7 (during single-chip mode) p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 2 to p7 7 , p8 0 to p8 4, p8 6, p8 7, p9 0 to p9 7, p10 0 to p10 7 (note 4) p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7, p6 0 to p6 7 , 10 5 ma f (x in ) mhz i ol (peak) ma i ol (avg) 16 f (xc in ) khz 50 32.768 v x in , reset, cnv ss , byte p0 0 to p0 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 2 to p7 7 , p8 0 to p8 4, p8 6, p8 7, p9 0 to p9 7, p10 0 to p10 7 p0 0 to p0 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 0 to p7 7 , p8 0 to p8 4, p8 6, p8 7, p9 0 to p9 7, p10 0 to p10 7 (note 4) p0 0 to p0 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 0 to p7 7 , p8 0 to p8 4, p8 6, p8 7, p9 0 to p9 7, p10 0 to p10 7 vcc=4.2v (note 1) to 5.5v 0.8vcc v v il symbol parameter unit standard min typ. max. supply voltage analog supply voltage supply voltage analog supply voltage high input voltage low input voltage high peak output current high average output current low peak output current low average output current main clock input oscillation frequency subclock oscillation frequency high input voltage v ih vcc p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7, p6 0 to p6 7 , x in , reset, cnv ss , byte p0 0 to p0 7 , p1 0 to p1 7 (during single-chip mode) low input voltage v il table 1.26.2. recommended operating conditions (referenced to v cc = 4.2v (note 1) to 5.5v at ta = C 40 o c to 125 o c (note 2) unless otherwise specified) note 1: in case of one-time prom version, 4.5v. note 2: in case of 85 c guaranteed version, - 40 c to 85 c. in case of 125 c guaranteed version, - 40 c to 125 c. note 3: the mean output current is the mean value within 100ms. note 4: in m30622(100-pin package), the total i ol (peak) and the total i oh (peak) for ports p0, p1, p2, p8 6 , p8 7 , p9, and p10 and the total i ol (peak) and the total i oh (peak) for ports p3, p4, p5, p6, p7, and p8 0 to p8 4 severally must be 80ma max. in m30623(80-pin package), vcc pin and vss pin are each one pin, so the total i ol (peak) and the total i oh (peak) for all ports must be 80ma max. note 5: the loss power effect of the whole part-port(the output port transistor and the pull-up resistor) must be 50mw max, so that power dissipation at ta=125 c(include ta >85 c) doesnt exceed absolute maximum ratings. note 6: in m30623(80-pin package), p1 0 to p1 7 , p4 4 to p4 7 ,p7 2 to p7 5 , and p9 1 are not connected to the external pin. x out v o p d 40? < ta ? 85? v v v v i avcc vcc t stg t opr mw v 300 p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 7 , p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 ,p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 ,p7 2 to p7 7 , p8 0 to p8 4, p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , reset, v ref , x in p9 0 to p9 7 , p10 0 to p10 7 p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 , cnv ss , byte p7 0 , p7 1 , v v av cc =v cc, av ss =v ss c c symbol parameter condition rated value unit supply voltage analog supply voltage input voltage output voltage power dissipation operating ambient temperature storage temperature p7 0 , p7 1 v av cc =v cc, av ss =v ss 0.3 to 7 0.3 to 6.5 (note 1) 200 300 200 85? 177 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development electrical characteristics table 1.26.3. electrical characteristics (referenced to v cc = 5v, v ss = 0v at ta = -40 o c to 125 o c (note 1) , f(x in ) = 16mh z unless otherwise specified) v oh v oh v oh v ol v ol v ol v v 0.9vcc v x out 3.0 3.0 v 0.4vcc v v x out 2.0 2.0 0.6vcc i ol =5ma vcc=4.0v to 5.5v i ol =1ma i ol =200a vcc=4.0v to 5.5v i ol =0.5ma p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 4 , p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 4 , highpower lowpower p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 highpower lowpower p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 4 , p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 4 , p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 v t+- v t- 0.2 0.8 v symbol parameter unit standard min typ. max. high output voltage high output voltage high output voltage low output voltage low output voltage low output voltage hysteresis i ih i il v ram icc v t+- v t- 0.5 1.5 v 5 ? 2 v 2 ? ma reset, cnvss, byte 50 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7, x in , reset, cnvss, byte v i =5v pull-up resistance v i =0v 28 38 f(x in )=16mhz, square wave, p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 0 to p7 7 , p8 0 to p8 7 , p9 0 to p9 7 , p10 0 to p10 7, x in , reset, cnvss, byte 4.0 ? f(x in )=16khz, square wave, 24 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 7 , p6 0 to p6 7 , p7 2 to p7 7 , p8 0 to p8 4 , p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 no pull-up resistance v i =0v hysteresis high input current low input current ram retention voltage power supply current ? when clock is stopped in single-chip mode, the output pins are open and other pins are vss diveide-by-1, no-wait f(x cin )=32khz ta=125 c when clock is stopped ta=25 c when clock is stopped measuring condition ta0 in to ta4 in , ta0 out to ta4 out, tb0 in to tb5 in , int 0 to int 5 , p8 2 to p8 4 , ad trg , cts 0 to cts 2 , clk 0 to clk4, rxd 0 to rxd 2, sin 3 , sin 4, ki 0 to ki 3, nmi when a wait instruction is executed, ta=25 c i oh = 5ma vcc=4.0v to 5.5v i oh = 200a vcc=4.0v to 5.5v i oh = 0.5ma i oh = 1ma 0.1vcc v t+- v t- x in hysteresis 0.2 0.8 v i il low input current ? 70 100 150 diveide-by-1, 1-wait f(x in )=16khz, square wave, 6.7 diveide-by-8, no-wait ma ma 5 x cout highpower lowpower high output voltage with no load applied with no load applied 3.0 1.6 v x cout low output voltage highpower lowpower with no load applied with no load applied 0 0 v r fxin r fxcin feedback resistance x in x cin feedback resistance 1.0 6.0 20 ta=85 c when clock is stopped m w m w note 1: in case of 85 c guaranteed version, - 40 c to 85 c. in case of 125 c guaranteed version, - 40 c to 125 c. note 2: in m30623(80-pin package), p1 0 to p1 7 , p4 4 to p4 7 ,p7 2 to p7 5 , and p9 1 are not connected to the external pin.
178 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development electrical characteristics table 1.26.4. a-d conversion characteristics (referenced to v cc = av cc = 5v, vss = av ss = 0v, ta = 25 o c, f(x in ) = 16mh z unless otherwise specified) ? standard min. typ. max. resolution absolute accuracy bits lsb v ref = v cc = 5 v ? 10 symbol parameter measuring condition unit v ref = av cc = v cc = 5 v , f ad 10mhz r ladder t conv ladder resistance conversion time (10bit) reference voltage analog input voltage k w v v ia v ref v 0 2 10 v cc v ref 40 conversion time (8bit) 3.3 t conv t samp sampling time 3.5 v ref = v cc = 5v sample & hold function not available sample & hold function available an 0 to an 7, an 00 to an 07, an 20 to an 27, anex 0 , anex 1 input external op-amp connection mode v ref =av cc =v cc =5v f ad 10mhz lsb lsb ? ? ? ? min. typ. max. t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % k w ma i vref 1.0 1.5 8 3 symbol parameter measuring condition unit 20 10 4 ? ( note 1 ) standard note 1: divide the frequency if f(x in ) exceeds 10 mhz, and make f ad equal to or lower than 10 mhz. (10bit) f(x in )=16mhz, f ad = f ad /2 = 8mhz 4.125 f(x in )=10mhz, f ad = f ad = 10mhz 0.375 0.3 f(x in )=16mhz, f ad = f ad /2 = 8mhz f(x in )=10mhz, f ad = f ad = 10mhz f(x in )=16mhz, f ad = f ad /2 = 8mhz f(x in )=10mhz, f ad = f ad = 10mhz 2.8 absolute accuracy(8bit) v ref = av cc = v cc = 5 v , f ad 10mhz lsb ? table 1.26.5. d-a conversion characteristics (referenced to v cc = 5v, v ss = av ss = 0v, v ref = 5v at ta = 25 o c, f(x in ) = 16mh z unless otherwise specified) note 1: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converter's ladder resistance is not included. note 2: when the vref is unconnected at the a-d control register, i vref is sent. when not using d-a converter, with the d-a register for the unused d-a converter set to 00 16 , so that prevent dissipation of unnecessary reference power supply current.
179 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development electrical characteristics max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 15 62.5 25 25 15 standard max. ns tai in input low pulse width t w(tal) min. ns ns unit tai in input high pulse width t w(tah) parameter symbol t c(ta) tai in input cycle time 60 150 60 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 400 200 200 standard max. min. ns ns ns unit tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter 200 100 100 standard max. min. ns ns unit t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width 100 100 standard max. min. ns ns ns unit ns ns symbol parameter tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 2000 1000 1000 400 400 standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width 250 250 timing requirements referenced to v cc = 5v, v ss = 0v at ta = -40 o c to 85 o c (85 o c guaranteed version), or ta = -40 o c to 125 o c (125 o c guaranteed version) unless otherwise specified. table 1.26.9. timer a input (gating input in timer mode) table 1.26.10. timer a input (external trigger input in one-shot timer mode) table 1.26.11. timer a input (external trigger input in pulse width modulation mode) table 1.26.12. timer a input (up/down input in event counter mode) table 1.26.8. timer a input (counter input in event counter mode) _______ table 1.26.7. external interrupt inti inputs table 1.26.6. external clock input
180 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development electrical characteristics timing requirements referenced to v cc = 5v, v ss = 0v at ta = - 40 o c to 85 o c(85 o c guaranteed version), or ta = - 40 o c to 125 o c(125 o c guaranteed version) unless otherwise specified. standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) 150 60 60 120 120 300 standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width 400 200 200 standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width 400 200 200 standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width 1000 125 ns ns ns ns ns ns ns standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi / s out i hold time rxdi / s in i input setup time txdi / s out i output delay time t h(c-d) rxdi / s in i input hold time 250 125 125 0 45 120 100 when external clock is selected when external clock is selected ns 120 when external clock is selected ns 45 when external clock is selected table 1.26.14. timer b input (pulse period measurement mode) table 1.26.15. timer b input (pulse width measurement mode) table 1.26.13. timer b input (counter input in event counter mode) table 1.26.17. a-d trigger input table 1.26.16. serial i/o
181 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development electrical characteristics figure 1.26.1. port p0 to p10 measurement circuit p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf timing
182 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development electrical characteristics tai in input t c(ta) t w(tah) t w(tal) tai out input t c(up) t w(uph) t w(upl) tbi in input t c(tb) t w(tbh) t w(tbl) t w(inl) t w(inh) inti input t c(ad) t w(adl) ad trg input during event counter mode t h(t in ?p) t su(up? in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) t su(d?) clki txdi / s out i rxdi / s in i t c(ck) t w(ckh) t w(ckl) t d(c?) t h(c?) t h(c?) v cc =5v figure 1.26.2. timing
183 tentative specifications rev.a mitsubishi microcomputers m16c / 62t group single-chip 16-bit cmos microcomputer s pecifications in this manual are tentative and subject to change. under development differences between m16c/62t group and m16c/61t group group m16c/62t group m16c/61t group serial i/o uart/clocked si/o ?????3 channel (80-pin package: one of exclusive uart) clocked si/o ???? 2 channel (80-pin package: one of exclusive transmission) uart/clocked si/o ?????3 channels (80-pin package: one of exclusive uart) port function p9 0 ?????tb0 in /clk3 p9 1 ?????tb1 in /s in 3 p9 2 ?????tb2 in /s out 3 p9 3 ?????tb3 in /da0 p9 4 ?????tb4 in /da1 p9 5 ?????anex0/clk4 p9 6 ?????anex1/s out 4 p9 7 ?????ad trg /s in 4 p1 5 ?????d13/int3 p1 6 ?????d14/int4 p1 7 ?????d15/int5 p7 1 ?????r x d 2 /ta0 in /tb5 in p9 0 ?????tb0 in p9 1 ?????tb1 in p9 2 ?????tb2 in p9 3 ?????da0 p9 4 ?????da1 p9 5 ?????anex0 p9 6 ?????anex1 p9 7 ?????ad trg p1 5 ?????d13 p1 6 ?????d14 p1 7 ?????d15 p7 1 ?????r x d 2 /ta0 in interrupt cause internal 20 sources external 5 sources software 4 sources internal 25 sources, external 8 sources (80-pin package: 5 sources), software 4 sources (added 2 serial i/o, 3 timers and 3external interrupts (note 2) ) three-phase inverter control circuit pwm output for three-phase inverter can be performed using timer a4, a1 and a2. output port is arranged to p7 2 to p7 5 , p8 0 and p8 1 . impossible iic bus mode uart2 used iic bus interface can be performed with software impossible memory space (note 1) memory expansion is possible 1.2m bytes mode 4m bytes mode 1m byte fixed timer b 6 channels 3 channels chip select cs0 : 30000 16 to fffff 16 cs1 : 28000 16 to 2ffff 16 cs2 : 08000 16 to 27fff 16 cs3 : 04000 16 to 07fff 16 m16c/61t type (wrinting the right) and the type as below can be switched (besides 4m-byte mode is possible.) cs0 : 04000 16 to 3ffff 16 (fetch) 40000 16 to fffff 16 (data/facth) cs1 : 28000 16 to 2ffff 16 (data) cs2 : 08000 16 to 27fff 16 (data) cs3 : 04000 16 to 07fff 16 (data) read port p1 by setting to register, the state of port register can be read always. the state of port when input mode. the state of port register when output mode. p4 4 /cs0 - p4 7 /cs3 if a vcc level is applied to the cnvss pin, bit 2 (pu11) of pull-up control register 1 turns to "1" when reset, and p4 4 / cs0 - p4 7 / cs3 turn involved in pull-up. bit 2 (pu11) of the pull-up control register 1 turns to "0" when reset, and p4 4 / cs0 - p4 7 / cs3 turn free from pull- up. (note 2) (note 2) (note 2) (note 2) (note 2) (note 2) (note 1) (note 2) (note 2) (note 2) (note 1) (note 2) note 1: m16c/61t group, and m16c/62t group are not guaranteed operating of memory expansion, but it is mentioned in the table for clear the difference of capacity. note 2: in 80-pin package(m30613, m30623), pins of a part are not connected to the external pin, so do not use these functions and pins.
mitsubishi semiconductors m16c/62t group tentative specification rev.a jan first edition 1999 editioned by committee of editing of mitsubishi semiconductor published by mitsubishi electric corp., kitaitami works this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1999 mitsubishi electric corporation

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